Services such as Internet protocol television (IPTV) not only accelerate bandwidth growth in the network, but also increase the demand for policing and scheduling the traffic on the network. Next-generation enterprise, metro, and core networks require high-speed traffic management solutions to deliver the bandwidth and intelligence necessary for delivering killer applications. Altera’s Stratix® IV GX FPGAs enable you to deliver 40-Gbps traffic management optimized for your specific application requirements.
The main bottleneck in developing high-speed traffic management solutions is the external memory bandwidth necessary to buffer the packets. In-line traffic management silicon must maintain memory throughput up to 3x the line rate for DDR technologies, and 2.5x the line rate for RLDRAM II technologies. A simplex 40-Gbps traffic manager could require up to 120 Gbps of external memory throughput, while a full-duplex traffic manager could require up to 240 Gbps. See Table 1.
| Table 1. External Memory Interface Requirements for 40G Traffic Management | ||||||||
| Function | Memory Type | BW Factor RD-WR+ Overhead | Raw Bandwidth Requirement (Gbps) |
Full Duplex (x2) Total Bandwidth Requirement (Gbps) |
Frequency (MHz) | Data Rate (Mbps) | Number of DIMM & I/O | Bandwidth Available (Gbps) |
|---|---|---|---|---|---|---|---|---|
| 40G Packet Buffer | DDR3 DRAM-based | 3x | 120G | 240G | 533 666 |
1,066 1,332 |
4 x 64b 4 x 64b |
270G 340G |
|
RLDRAM II-based |
2.5x | 100 | 200 | 400 500 |
800 1,000 |
4 x 72b 4 x 72b |
230G 288G |
|
| 40G Queue Memory | QDR II+ | 1x | 40G | 80G | 400 | 800 | 3 x 36b | 90G |
Altera’s Stratix IV GX FPGAs are optimized to support the external memory interfaces necessary for full-duplex 40G traffic management. See Table 2.
| Table 2. Stratix IV FPGA Maximum Clock Rate Support for External Memory Interfaces | ||
| Memory Type | Maximum Data Rate (Per Pin) | Maximum Clock Frequency |
|---|---|---|
| DDR3 SDRAM | 1,067 Mbps | 533 MHz |
| DDR2 SDRAM | 800 Mbps | 400 MHz |
| DDR SDRAM | 400 Mbps | 200 MHz |
| RLDRAM II | 800 Mbps | 400 MHz |
| QDR II+ SRAM | 1,400 Mbps | 350 MHz |
| QDR II SRAM | 1,400 Mbps | 350 MHz |
Complex scheduling algorithms must be processed real-time in hardware. Altera’s programmable silicon can be optimized for varying requirements across applications, geographies, and customers. The Stratix IV architecture is built to support 40 Gbps and above datapaths in the core fabric. Stratix IV FPGAs leverage Altera's highly successful and innovative adaptive logic module (ALM) logic structure to provide the most efficient logic fabric ever in any 40-nm FPGA.
As datapath designs advance beyond 10 Gbps, the chip-to-chip interfaces have moved from LVDS-based I/O standards such as SPI-4.2 to serial-based standards such as Interlaken (see Figure 1). The integrated high-speed transceivers in Stratix IV FPGAs allow the traffic manager to meet the chip-to-chip interface requirements for these 40-Gbps cards as well as the high-speed backplane requirements that reduce the overall cost and board space in the system.
Figure 1. Example Networking Card
HardCopy ASIC Solutions
In addition to the programmable solutions of Stratix IV FPGAs, Altera also provides a cost-optimized HardCopy® IV ASIC.
HardCopy IV ASICs deliver the lowest risk, lowest total cost, fastest time-to-market, and fastest time-to-profit solution for your custom logic needs. HardCopy IV ASICs come in two variants:
- HardCopy IV E devices focus on logic, memory, and/or digital signal processing (DSP)-rich applications
- HardCopy IV GX devices focus on applications requiring high-speed transceivers
Delivering all of the excellent transceiver performance and signal integrity you expect from Altera, HardCopy IV GX devices contain up to 24 transceivers, up to 12M ASIC gates, and up to 13.3 Mbits of SRAM. High-performance computing, high-reliability computing, storage, military, and, of course, wireless and wireline markets all have many applications requiring high-speed transceivers.
Spanning the range of up to 24 transceivers, 13.7 to 2.8 million usable ASIC gates, and 16.4 to 5.4 Mbits of memory, HardCopy IV ASICs can service a wide range of applications.
