Services such as Internet protocol television (IPTV) accelerate bandwidth growth in the network, and also increase the demand for policing and scheduling the traffic on the network. Next-generation enterprise, metro, and core networks require high-speed traffic management solutions to deliver the bandwidth and intelligence necessary for delivering killer applications. Altera's Stratix® series FPGAs enable you to deliver 40-Gbps and 100-Gbps traffic management optimized for your specific application requirements.
The main bottleneck in developing high-speed traffic management solutions is the external memory bandwidth necessary to buffer the packets. In-line traffic management silicon must maintain memory throughput up to 3X the line rate for DDR technologies, and 2.5X the line rate for RLDRAM II technologies. A simplex 40-Gbps traffic manager could require up to 120 Gbps of external memory throughput, while a full-duplex traffic manager could require up to 240 Gbps. See Table 1.
|Table 1. External Memory Interface Requirements for 40G Traffic Management|
|Function||Memory Type||BW Factor RD-WR+ Overhead||Raw Bandwidth
|Full Duplex (x2) Total
Bandwidth Requirement (Gbps)
|Frequency (MHz)||Data Rate (Mbps)||Number of DIMM and I/Os||Bandwidth Available (Gbps)|
|40G Packet Buffer||DDR3 DRAM-based||3X||120G||240G||533
|4 x 64b
4 x 64b
|4 x 72b
4 x 72b
|40G Queue Memory||QDR II+||1X||40G||80G||400||800||3 x 36b||90G|
Altera's Stratix series FPGAs are optimized to support the external memory interfaces necessary for full-duplex 40G and 100G traffic management.
Complex scheduling algorithms must be processed real-time in hardware. Altera's programmable silicon can be optimized for varying requirements across applications, geographies, and customers. The Stratix architecture is built to support 100 Gbps and above datapaths in the core fabric. Stratix series FPGAs leverage Altera's highly successful and innovative adaptive logic module (ALM) logic structure to provide the most efficient logic fabric ever in any 40-nm FPGA.
As datapath designs advance beyond 10 Gbps, the chip-to-chip interfaces have moved from LVDS-based I/O standards such as SPI-4.2 to serial-based standards such as Interlaken (see Figure 1). The integrated high-speed transceivers in Stratix series FPGAs allow the traffic manager to meet the chip-to-chip interface requirements for these 40-Gbps cards as well as the high-speed backplane requirements that reduce the overall cost and board space in the system.
Figure 1. Example Networking Card
HardCopy ASIC Solutions
In addition to the programmable solutions of Stratix series FPGAs, Altera also provides a cost-optimized HardCopy® ASIC.
HardCopy series ASICs deliver the lowest risk, lowest total cost, fastest time-to-market, and fastest time-to-profit solution for your custom logic needs.