SDRAM Controller in the (DAC)
The SDRAM controller provides a handshaking protocol to the processor and a standard interface to the SDRAM. This example requires 32 Mbytes of off-chip SDRAM. The SDRAM controller allows programmable or constrained timing, bank management, and bus cascading. The controller supports up to eight banks of memory with two Gbytes of memory space and has a maximum speed of 133 MHz in an APEX™ II device (in single data rate mode). A special interface for the 32-bit MIPS processor to the SDRAM controller is required to complete the integration of the processor and the SDRAM controller.