The processor function is modeled on the 32-bit MIPS-based instruction set with an R3000-class architecture. This processor function is capable of operating at 33 MHz on an Altera®APEX™ II device and executes instructions over a five-stage pipeline. All transactions within the processor function and its interfaces occur on the positive edge of the processor clock, and do not require two-phase clocks for implementation. This means that results the processor function does not use on-chip phase-locked loops (PLLs). The processor function selected for this example is the LX-4180 from AMPP partner, Lexra.
The processor function receives packetized information from the frame relay network and determines where to route the signal based on the phone number dialed (outgoing) or the Internet protocol address (incoming). The processor function also supplies control information to peripheral cores including the tone generation function, the signal detection logic, and the synchronous dynamic random access memory (SDRAM) controller functions. The processor function does not have access to the packet bus, which is reserved for communication between the digital access cards (DACs).
The system supports all 32-bit co-processor operations, including moves to and from the co-processor's general registers and control registers. The co-processor loads and stores based on the co-processor condition flags. All co-processor operations execute in a single clock cycle without pipeline stalls. The processor function also features configurable cache sizes and separate data and instruction memory spaces, which are implemented using embedded system blocks (ESBs) in the APEX II device.