Wireline Webcasts and Videos | |
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Balancing Power, Performance, and Cost with Arria V FPGAs View this webcast to learn how Arria® V FPGAs have been optimized to improve power consumption and save cost without sacrificing performance. You’ll learn about the new 28-nm core architecture and how the use of the 28-nm Low-Power (28LP) process and other unique innovations significantly improves your power consumption and saves you cost. Martin Won, Senior Member of Technical Staff |
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Sneak Peek: Industry’s First 28-Gbps FPGA Watch this 5-minute video to see the performance of our 28-nm Stratix® V FPGA transceiver. You will see the transmit eye diagram at 28 Gbps running a PRBS-31 pattern and the receiver performance at 28 Gbps. You will also learn about the transceiver architecture that provides high performance, power efficiency, and reliability. Salman Jiva, Technical Manager, High-End FPGAs |
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5 Reasons to Use a Soft-Core MIPS Processor in Your Next Custom Design Watch this video to learn five reasons why you should use a soft-core MIPS processor in your next custom design. You'll get insights about the MP32 processor, the first 100 percent MIPS-compatible soft processor available for Altera® FPGAs and HardCopy® ASICs. Cal Ruben, Applications Engineer, Embedded Technology |
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Sneak Peek: Industry's First 28-nm High-End FPGA Running at 14.1 Gbps Watch this video to see the progress of the Stratix V FPGA characterization process, as well as 14.1-Gbps transceiver performance. Stratix V FPGAs are the industry's first 28-nm high-end FPGAs. Salman Jiva, Applications Manager |
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Make Music and More with Low-Cost, Low-Power CPLD Dev Kit This video demonstrates the various capabilities of the MAX V CPLD Development Kit. Available for only $74.95, the kit gives you the resources to evaluate the MAX V CPLD and to prototype CPLD applications. Jenny Gendron, Altera |
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Enhance Your Productivity with Faster Design Compile Times When choosing your FPGA design software, be sure to consider compile time, a key productivity advantage. In this webcast, you'll learn how Altera's Quartus® II design software delivers a 2X to 3X compile time advantage over competitive software. Richard Yang, Product Marketing Engineer |
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Lower Power and Boost System Bandwidth on 28-nm FPGAs Learn about key innovations in Stratix® V FPGAs that address bandwidth and power challenges in high-end systems designs. Embedded HardCopy Blocks, power-efficient 28-Gbps transceivers, and software power optimization are just a few of the features that will help you balance bandwidth, power, and cost requirements. Frank Yazbeck, Senior Technical Marketing Staff |
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Achieving 25-Gbps Transceiver Performance on 28-nm FPGAs Watch this 9-minute video to see a live demo of our 28-nm transceiver technology running a pseudo-random bit pattern at 25-Gbps. You'll also view TX and RX eye diagrams across at 10GBASE-KR backplane running at 10 Gbps, and learn more about Stratix V FPGAs. Allan Davidson, Product Marketing Manager |
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See 40-Gbps OTN Mapper and EFEC Demo Using High-Density 40-nm FPGA Find out how to develop telecom applications that’s both low in cost and power requirements. Learn about our 40-nm Stratix IV GX FPGA, which has up to 530K logic elements and on-chip serial interfaces and see our partner TPACK’s TPO314 optical transport network (OTN) mapping product in action. Jeff Wimett, Applications Engineer |
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See 100G Interlaken Demo on 40-nm High-Density FPGA This webcast shows the design advantages of the 40-nm Stratix IV GT FPGAs and the Altera Interlaken solution running on our 100G demo board. Learn how you can use our 10G Transceiver Signal Integrity Kit, Stratix IV GT Edition to evaluate signal integrity and to generate and monitor pseudo-random binary sequence (PRBS) patterns. Rishi Chugh, Product Marketing Manager |
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