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Home > Products > Devices > HardCopy Stratix Print This Page Subscribe to Email HardCopy Stratix Devices About These Devices Power Estimator About HardCopy HardCopy II ASICs Features View the Flash Demo HardCopy Stratix ASICs The HardCopy® Stratix® family features a unique FPGA front-end design methodology to deliver the lowest-risk, fastest time-to-market solution in the industry. Test your designs with Stratix FPGAs, then Altera’s HardCopy Design Center seamlessly migrates the designs to a low-cost, functionally-equivalent, pin-compatible HardCopy Stratix device. The HardCopy Stratix family delivers: 0.13-μm technology with two-layer metal customization Up to 50 percent performance improvement compared to Stratix FPGAs Up to 40 percent core power reduction (dynamic and static) compared to the Stratix FPGA in which the design was tested See the Stratix II and HardCopy II device pages for details on the latest devices, which provide the highest performance and density with a path to HardCopy ASICs for low cost and low risk. HardCopy Stratix devices preserve the architecture and features of Stratix FPGAs. See detailed descriptions of the HardCopy Stratix devices, resources, and packaging on the HardCopy Stratix Overview page. Complete Prototype-to-Production Platform Create designs using existing development tools, including standard EDA tools from Cadence, Mentor Graphics® , or Synopsys design software with Altera's Quartus® II software, then verify the design in-system with a Stratix FPGA. Altera then migrates the Stratix FPGA design to a pin-compatible, functionally-equivalent HardCopy ASIC. There is no need to re-spin the board. You get guaranteed, fully operational prototypes in record time, minimizing risk and helping you get to market as quickly as possible. HardCopy Stratix ASICs enable you to: Get your products to market 6 to 9 months earlier than standard-cell technology flow Create your first product at a fraction of the traditional development cost Demonstrate designs to customers in Stratix FPGAs before committing to ASIC silicon Introduce multiple product variations, customized to different market needs, at the same time Move from prototype to low-cost production quickly, while minimizing cost and engineering effort Table 1 highlights several powerful HardCopy migration features available in the Quartus II software. Table 1. HardCopy-Related Features in the Quartus II Software Feature Description HardCopy Floorplan Editor & Timing Models Targets designs to HardCopy devices and estimates device performance and power consumption. Allows you to view the actual placement of your design in the floorplan. Design Assistant Ensures that the design is compliant with HardCopy design rules to facilitate a smooth migration. HardCopy Timing Optimization Wizard Provides the ability to improve the HardCopy device's performance and power consumption. HardCopy Files Wizard Assembles all the required deliverables for migration to a HardCopy device. PowerPlay Early Power Estimator Allows the designer to estimate power consumption for HardCopy devices without using simulation vectors. Related Links About HardCopy Series HardCopy Stratix Overview HardCopy II ASICs HardCopy Literature Quartus II Software Support Stratix FPGAs Rate This Page   Next Steps Download Software Get Training Support Read Success Stories Join the Altera Forum Get Device Support View Knowledge Database Documentation Get Literature Get Handbook (PDF) Get Data Sheet (PDF) Get Email Updates Get Product Catalog (PDF)

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