Intel® MAX® 10 FPGA – AN 498: LED Blink Using Power Sequencing Design Example

Intel® MAX® 10 FPGAs are well suited for this due to their simple power sequencing and proprietary features. This application note illustrates a simple method for blinking an LED by using the auto stop and auto start capability of Intel MAX 10 FPGAs.

Many consumer and industrial application systems do not require the FPGA to be powered on at all times. In fact, it is preferable to have a system in which the FPGA powers on intermittently, as and when required only, and remains off for most of the cycle. Intel MAX 10 FPGAs are designed to tolerate any possible power-on sequence. They also have one of the industry's lowest power-up timing characteristics (typically 200 microseconds for the EPM240 device, depending on the density of logic in the design).

This makes Intel MAX 10 FPGAs the perfect target device for such a system. The FPGA can be turned off when a task is complete and switched back on again for its next task. The self power down is caused by the FPGA itself, while the auto power up is caused by an external circuitry such as a simple RC circuit designed for the required delay. The entire scheme finds context in power savings, typically in battery operated systems which may be used for functions that are cyclical or periodic in nature (such as sampling for parameters in a telemetering system), where the power can be turned off when the FPGA can afford to take a break.

The FPGA generates two signals, power down and its complement to cause self power down by triggering an external circuit to shutdown the LDO supplying power to the FPGA. After the FPGA is off, the external circuit powers it back on after the designed delay of the external RC circuit. An LED glows upon power on and switches off after the FPGA is powered down.

Prepare the design template in the Quartus Prime software GUI (version 14.1 and later)

Note: After downloading the design example, you must prepare the design template. The file you downloaded is of the form of a <project>.par file which contains a compressed version of your design files (similar to a .qar file) and metadata describing the project. The combination of this information is what constitutes a <project>.par file. In releases 16.0 or newer, you can simply double click on the <project>.par file and Quartus will launch that project.

The second means to bring up the project template is through the New Project Wizard (File -> New Project Wizard). After entering the project name and folder on the first panel, the second panel will ask you to specify an empty project or project template. Select project template. You will see a list of Design Templates projects that you have loaded prior as well as various "Baseline Pinout Designs" that contain the pinout and settings for a variety of development kits. If you don't see your design template in the list, click on the link that states install the Design Templates circled below:

Browse to the <project>.par file you downloaded, click next, followed by Finish, and your design template will be installed and displayed in the Project Navigator pane in Quartus.

Note: When a design is stored in the Design Store as a design template, it has been previously regression tested against the stated version of Quartus software. The regression ensures the design template passes analysis/synthesis/fitting/assembly steps in the Quartus design flow.

Prepare the design template in the Quartus Prime software command-line

At the command-line, type the following command:

quartus_sh --platform_install -package <project directory>/<project>.par

Once the process completes, then type:

quartus_sh --platform -name <project>