This design example is to implement a SERDES using the Cyclone II architecture.  The designs are in Verilog and BDF format and has the following file structure:

cyc2_ch_11_x8_mode
   - BDF
      - HSIO_RX.qar
      - HSIO_TX.qar
      - x8_mode_top.qar
   - Verilog
      - HSIO_RX.qar
      - HSIO_TX.qar
      - x8_mode_top.qar

The HSIO_RX.qar files contain files to implement a simple receiver.
The HSIO_TX.qar files contain files to implement a simple transmitter.
The x8_mode_top.qar files implement a transceiver by instantiating HSIO_RX and HSIO_TX.

This design uses LSB first convention but can be easily modifed for MSB first.  A simple simulation is included to illustrate functionality.  Note that for a full design a byte realigner will have to be used to ensure that the byte deserialized out of the receiver has the correct alignment.  This design did not implement a byte realigner and therefore the parallel data transmitted out and the parallel data received have different byte alignments.