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Literature: Application Notes

Home > Products > Literature > Application Notes

Note: Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera Corporation. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

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Title Doc Version Release Date File Size Document Part Number
Application Notes
Subscribe Alert AN 605: Using the EyeQ Feature in Stratix IV Transceivers New
     Stratix IV GX Board EyeQ Reference Design (1 MB)
1.0Mar 2010962 KBAN-605-1.0
Subscribe Alert AN 601: Serial Digital Interface Reference Design for Arria II GX Devices New
     Design Files for AN 601 (3 MB)
1.1Feb 2010582 KBAN-601-1.1
Subscribe Alert AN 597: Getting Started Flow for Board Designs Updated 1.1Mar 2010161 KBAN-597-1.1
Subscribe Alert AN 596: Modeling and Design Considerations for 10 Gbps Connectors New
     an596_stateye_examples.zip (120 KB)
1.0Mar 20101 MBAN-596-1.0
Subscribe Alert AN 592: Cyclone IV Design Guidelines Updated 1.1Jan 2010392 KBAN-592-1.1
Subscribe Alert AN 580: Achieving Timing Closure in Basic (PMA Direct) Functional Mode Updated
     AN580_scripts.zip (17 KB)
2.0Feb 2010423 KBAN-580-2.0
Subscribe Alert AN 558: Implementing Dynamic Reconfiguration in Arria II GX Devices Updated 2.1Jan 20103 MBAN-558-2.1
Subscribe Alert AN 554: How to Read HardCopy PrimeTime Timing Reports Updated 2.0Mar 2010554 KBAN-554-2.0
Subscribe Alert AN 550: Using the DLL Phase Offset Feature in Stratix FPGAs and HardCopy ASICs Updated
     altmemphy_ext_dll.zip (48 KB)
     altmemphy_int_dll.zip (47 KB)
     static_dll.zip (18 KB)
2.0Mar 2010547 KBAN-550-2.0
Subscribe Alert AN 540: Nios II MPU Usage New
     Design Files for AN 540 (221 KB)
1.0Mar 2010385 KBAN540-1.0
Subscribe Alert AN 461: Design Guidelines for Implementing QDRII+ and QDRII SRAM Interfaces in Stratix III and Stratix IV Devices Updated
     Design Example for AN 461 (3 MB)
1.2Feb 2010986 KBAN-461-1.2
Subscribe Alert AN 459: Guidelines for Developing a Nios II HAL Device Driver Updated
     AN 459 Design Example (52 KB)
3.0Jan 2010964 KBAN-459-3.0
Subscribe Alert AN 433: Constraining and Analyzing Source-Synchronous Interfaces Updated 2.2Mar 20102 MBAN-433-2.2
AN 432: Using Different PLL Settings Between Stratix II and HardCopy II Devices Updated 1.2Mar 2010149 KBAN-432-1.2
Subscribe Alert AN 431: PCI Express to External Memory Reference Design Updated 1.3Feb 2010408 KBAN-431-1.3
Subscribe Alert AN 600: Serial Digital Interface Reference Design for Stratix IV Devices
     Design Files for AN 600 (1 MB)
1.0Dec 2009586 KBAN-600-1.0
Subscribe Alert AN599: Arria II GX RapidIO Interoperability with TI 6488 DSP Reference Design1.0Dec 20091,019 KBAN-599-1.0
Subscribe Alert AN 595: Vectored Interrupt Controller Usage and Applications
     Example Designs for AN595 (503 KB)
1.0Nov 2009246 KBAN595-1.0
Subscribe Alert AN 593: Anti-Tamper Protection for Cyclone III LS Devices1.0Oct 2009626 KBAN-593-1.0
Subscribe Alert AN 589: Using the Design Security Feature in Cyclone III LS Devices1.0Sep 20091 MBAN-589-1.0
Subscribe Alert AN 588: 10-Gbps Ethernet Hardware Demonstration Reference Design1.1Dec 20091 MBAN-588-1.1
Subscribe Alert AN587: DPRIO and Multiple Instances SDI Application1.0Aug 20091,002 KBAN-587-1.0
Subscribe Alert AN 586: Porting the Jam STAPL and Jam STAPL Byte-Code Players to an Embedded System1.0Aug 2009176 KBAN-586-1.0
Subscribe Alert AN585: Simulation Debugging Using Triple Speed Ethernet Testbench
     AN585: Test Cases (3 MB)
1.0Aug 2009368 KBAN-585-1.0
Subscribe Alert AN 584: Timing Closure Methodology for Advanced FPGA Designs
     AN 584: Design Examples (380 KB)
1.0Aug 20091 MBAN-584-1.0
Subscribe Alert AN 583: Designing Power Isolation Filters with Ferrite Beads for Altera FPGAs
     AN 583: VCC to VCCDPLL Spice Examples (159 KB)
1.0Jul 2009889 KBAN-583-1.0
AN 581: High Definition Video Reference Design (V2)1.0Nov 20091 MBAN-581-1.0
Subscribe Alert AN 578: Manual Placement of CMU PLLs and ATX PLLs in Stratix IV GX and GT Devices1.0May 20091 MBAN-578-1.0
Subscribe Alert AN 577: Recommended Protocol Configurations for Stratix IV GX FPGAs2.0Dec 2009753 KBAN-577-2.0
Subscribe Alert AN 574: Printed Circuit Board (PCB) Power Delivery Network (PDN) Design Methodology1.0May 2009899 KBAN-574-1.0
Subscribe Alert AN 573: Implementing the Interlaken Protocol in Stratix IV Transceivers
(Not applicable when designing with Stratix IV GX and Stratix IV GT engineering sample devices)
1.1Dec 2009768 KBAN-573-1.1
Subscribe Alert AN 572: Implementing the Scalable SERDES Framer Interface (SFI-S) Protocol in Stratix IV GT Devices
(Not applicable when designing with Stratix IV GT engineering sample devices)
2.0Jan 2010284 KBAN-572-2.0
Subscribe Alert AN 571: Implementing the SERDES Framer Interface Level 5 (SFI-5.1) Protocol in Stratix IV Devices1.0Jun 2009549 KBAN-571-1.0
Subscribe Alert AN 570: Implementing the 40G/100G Ethernet Protocol in Stratix IV Devices
(Not applicable when designing with Stratix IV GT engineering sample devices)
1.1Dec 20091 MBAN-570-1.1
Subscribe Alert AN 569: SDI Flywheel Video Decoder Reference Design1.0May 20091 MBAN-569-1.0
Subscribe Alert RapidIO Interoperability with TI 6488 DSP Reference Design
(AN568: RapidIO Interoperability with TI 6488 DSP Reference Design)
1.0May 2009883 KBAN568-1.0
Subscribe Alert AN 567: Quartus II Design Separation Flow1.0Jun 20093 MBAN-567-1.0
Subscribe Alert AN 563: Arria II GX Design Guidelines1.0Feb 2009752 KBAN-563-1.0
Subscribe Alert AN561: Stratix II GX 10GbE Loopback Reference Design1.1Oct 2009549 KBAN-561-1.1
AN 559: High Definition Video Reference Design (V1)1.0Dec 20081 MBAN-559-1.0
Subscribe Alert AN557: Stratix III to Stratix IV E Cross-Family Migration Guidelines2.0Sep 2009924 KBAN-557-2.0
Subscribe Alert AN556: Using the Design Security Feature in Arria II GX and Stratix IV Devices1.1Jun 20091 MBAN-556-1.1
Subscribe Alert AN 553: Debugging Transceivers
     AN 553: Design Files (874 KB)
1.1Dec 20091 MBAN-553-1.1
AN 551: SDI-ASI Auto Detect Reference Design for Stratix II GX Devices1.0Nov 2008232 KBAN-551-1.0
AN 549: Managing Designs with Multiple FPGAs1.0Sep 2008776 KBAN-549-1.0
AN 548: Nios II Compact Configuration System for Cyclone III
     Design Files for AN 548 (597 KB)
1.0Nov 2008320 KBAN-548-1.0
Subscribe Alert AN 547: Putting the MAX II CPLD in Hibernation Mode to Achieve Zero Standby Current
     MAX II Hibernation Design (87 KB)
1.0Jan 2009256 KBAN-547-1.0
Subscribe Alert AN 545: Design Guidelines and Timing Closure Techniques for HardCopy ASICs
     Example_design.zip (578 KB)
2.0Dec 20092 MBAN-545-2.0
AN 544: Digital IF Modem Design with the DSP Builder Advanced Blockset1.0Aug 2008976 KBAN-544-1.0
Subscribe Alert AN543: Debugging Nios II Software Using the Lauterbach Debugger
     Example Design for AN543 (6 MB)
1.0Apr 2009278 KBAN543-1.0
AN 542: High Definition Video Monitoring Reference Design (M5)1.2Nov 2008814 KBAN-542-1.2
AN 541: SerialLite II Hardware Debugging Guide1.0Aug 20081 MBAN-541-1.0
Subscribe Alert AN539: Test Methodology of Error Detection and Recovery using CRC in Altera FPGA Devices
     AN539 Design Example (425 KB)
1.1Jan 2009406 KBAN-539-1.1
AN 537: Implementing UNH-IOL Test Suite Compliance in Arria GX and Stratix II GX Gigabit Ethernet Designs
     carrier_detect_logic.zip (2 KB)
1.0Sep 2008514 KBAN-537-1.0
AN 536: Design Guidelines for Preparing HardCopy II ASICs1.0Sep 20081 MBAN-536-1.0
Subscribe Alert AN 533:Automotive Information and Entertainment Reference Designs1.3Nov 20093 MBAN-533-1.3
AN 532: An SOPC Builder PCI Express Design with GUI Interface
     Design Files for AN 532 (5 MB)
1.0Jun 2008285 KBAN-532-1.0
AN 531: Reducing Power with Hardware Accelerators
     Design Files for AN 531 (1 MB)
1.0May 2008151 KBAN-531-1.0
Subscribe Alert AN 530: Optimizing Impedence Discontinuity Caused by Surface Mount Pads for High-Speed Channel Designs1.0May 2008208 KBAN-530-1.0
Subscribe Alert AN 529: Via Optimization Techniques for High-Speed Channel Designs1.0May 2008690 KBAN-529-1.0
Subscribe Alert AN 528: PCB Dielectric Material Selection and Fiber Weave Effect on High-Speed Channel Routing1.0May 20081 MBAN-528-1.0
AN527: Implementing an LCD Controller1.0May 2008344 KBAN-527-1.0
Subscribe Alert AN 526: 3GPP UMTS Turbo Reference Design2.0Jan 2010374 KBAN-526-2.0
AN 524: High Definition Video Monitoring Reference Design (M4)1.0Apr 2008567 KBAN-524-1.0
Subscribe Alert AN523: Cyclone III Configuration Interface Guidelines with EPCS Devices1.1Jun 2009966 KBAN-523-1.1
Subscribe Alert AN 522: Implementing Bus LVDS Interface in Supported Altera Device Families
     Design Examples for AN 522 (37 KB)
2.0Nov 2009856 KBAN-522-2.0
Subscribe Alert AN 521: Cyclone III Active Parallel Remote System Upgrade Reference Design
     AN521 Design Files (1 MB)
1.1Aug 2009994 KBAN-521-1.1
Subscribe Alert AN 520: DDR3 SDRAM Memory Interface Termination and Layout Guidelines1.1May 2009909 KBAN-520-1.1
Subscribe Alert AN 519: Stratix IV Design Guidelines1.1May 2009493 KBAN-519-1.1
AN 518: SGMII Interface Implementation Using Soft-CDR Mode of Stratix III Devices1.0May 20081 MBAN-518-1.0
AN 517: Using High-Performance DDR, DDR2, DDR3 SDRAM with SOPC Builder
     AN 517 Design Files (2 MB)
1.0Apr 20081 MBAN-517-1.0
AN 515: 24K FFT for 3GPP LTE RACH Detection1.0Nov 2008230 KBAN-515-1.0
Subscribe Alert AN 514: Power Optimization in Stratix IV FPGAs1.0May 2008221 KBAN-514-1.0
AN 513: RapidIO Interoperability With TI 6482 DSP Reference Design2.0Nov 2008867 KBAN-513-2.0
Subscribe Alert AN 512: Using the Design Security Feature in Stratix III Devices1.1Mar 20091 MBAN-512-1.1
AN 511: Polyphase Modulation Using a FPGA for High-Speed Applications1.0Feb 2008279 KBAN-511-1.0
AN 509: Multiplexing SDIO Devices Using MAX II CPLDs
     AN 509 Design Example (721 KB)
1.0Dec 2007198 KBAN-509-1.0
AN 508: Cyclone III Simultaneous Switching Noise (SSN) Design Guidelines1.0Dec 2007379 KBAN-508-1.0
AN 507: Implementing PLL Reconfiguration in Cyclone III Devices
     Design Example 1: an507_de1_display.zip (204 KB)
     Design Example 2: an507_de2_dynphase.zip (84 KB)
1.0Jan 2008739 KBAN-507-1.0
AN 506: QR Matrix Decomposition2.0Mar 2008371 KBAN-506-2.0
Subscribe Alert AN 505: 3GPP LTE Turbo Reference Design2.0Jan 2010388 KBAN-505-2.0
AN 504: DSP System Design in Stratix III Devices
     Design Example 1: Parallel FIR (79 KB)
     Design Example 2: Multi-Channel FIR (20 KB)
     Design Example 3: MAC_FIR (vhdl) (21 KB)
     Design Example 4: Large Mult_Add (11 KB)
1.0Feb 20081 MBAN-504-1.0
AN 503: Implementing OFDM Modulation for Wireless Communications1.0Jan 2008268 KBAN-503-1.0
AN 502: Implementing an SMBus Controller in MAX II CPLDs
     AN 502 Design Example (2 MB)
1.0Dec 2007129 KBAN-502-1.0
AN 501: Pulse Width Modulation Using MAX II CPLDs
     AN 501 Design Example (279 KB)
1.0Dec 2007104 KBAN-501-1.0
AN 500: NAND Flash Memory Interface with MAX II CPLDs
     AN 500 Design Example (187 KB)
1.0Dec 2007137 KBAN-500-1.0
AN 499: Mobile SDRAM Interface Using MAX II CPLDs
     AN 499 Design Example (450 KB)
1.0Dec 2007109 KBAN-499-1.0
AN 498: LED Blink Using Auto Stop and Auto Start in MAX II CPLDs
     AN 498 Design Example (168 KB)
1.0Dec 2007104 KBAN-498-1.0
AN 497: LCD Controller Using MAX II CPLDs
     AN 497 Design Example (2 MB)
1.0Dec 2007133 KBAN-497-1.0
AN 496: Using the Internal Oscillator in MAX II CPLDs
     AN 496 Design Example (230 KB)
1.0Dec 2007362 KBAN-496-1.0
AN 495: IDE/ATA Controller Using MAX II CPLDs
     AN 495 Design Example (418 KB)
1.0Dec 2007155 KBAN-495-1.0
AN 494: GPIO Pin Expansion Using I2C Bus Interface in MAX II CPLDs
     AN 494 Design Example (273 KB)
1.0Dec 2007193 KBAN-494-1.0
AN 493: I2C Battery Gauge Interface Using MAX II CPLDs
     AN 493 Design Example (465 KB)
1.0Dec 2007171 KBAN-493-1.0
AN 492: CF+ Interface Using MAX II CPLDs
     AN 492 Design Example (346 KB)
1.0Dec 2007145 KBAN-492-1.0
AN 491: Auto Start Using MAX II CPLDs
     AN 491 Design Example (245 KB)
1.0Dec 2007119 KBAN-491-1.0
AN 490: MAX II CPLDs as Voltage Level Shifters
     AN 490 Design Example (147 KB)
1.0Dec 2007323 KBAN-490-1.0
AN 489: Using the UFM in MAX II Devices
     AN 489 Design Example (551 KB)
1.0Dec 2007161 KBAN-489-1.0
AN 488: Stepper Motor Controller Using MAX II CPLDs
     AN 488 Design Example (350 KB)
1.0Dec 2007100 KBAN-488-1.0
AN 487: SPI to I2S Using MAX II CPLDs
     AN 487 Desgin Example (589 KB)
1.0Dec 2007138 KBAN-487-1.0
AN 486: SPI to I2C Using MAX II CPLDs
     AN 486 Design Example (385 KB)
1.0Dec 2007144 KBAN-486-1.0
AN 485: Serial Peripheral Interface Master in MAX II CPLDs
     AN 485 Design Example (305 KB)
1.0Dec 2007117 KBAN-485-1.0
AN 484: SMBus for GPIO Pin Expansion in MAX II CPLDs
     AN 484 Design Example (2 MB)
1.0Dec 2007120 KBAN-484-1.0
Subscribe Alert AN 483: Triple Speed Ethernet Data Path Reference Design 1.1Jun 20092 MBAN-483-1.1
AN 482: High Definition Video Monitoring Reference Design (M2)4.0Aug 2008621 KBAN-482-4.0
AN 481: Applying Multicycle Exceptions in the TimeQuest Timing Analyzer1.0Jul 20082 MBAN-481-1.0
AN 480: 1536-Point FFT for 3GPP Long Term Evolution1.0Oct 2007154 KBAN-480-1.0
Subscribe Alert AN 479: Design Guidelines for Implementing LVDS Interfaces in Cyclone Series Devices1.1Jun 2009435 KBAN-479-1.1
AN 478: Using FPGA-Based Parallel Flash Loader with the Quartus II Software1.0Nov 2007861 KBAN-478-1.0
Subscribe Alert AN 477: Designing RGMII Interface with FPGA and HardCopy Devices2.0Jan 2010519 KBAN-477-1.0
AN 476: Impact of I/O Settings on Signal Integrity in Stratix III Devices1.0Oct 2007391 KBAN-476-1.0
AN 475: Crest Factor Reduction for OFDMA Systems1.0Dec 2007362 KBAN-475-1.0
AN 474: Implementing Stratix III Programmable I/O Delay Settings in the Quartus II Software1.2Mar 2008365 KBAN-474-1.2
AN 472: Stratix II GX SSN Design Guidelines1.0Aug 2007666 KBAN-472-1.0
AN 471: High-Performance FPGA PLL Analysis with TimeQuest1.0Aug 2007227 KBAN-471-1.0
AN 469: Stratix III Design Guidelines1.1May 2008628 KBAN-469-1.1
AN 466: Cyclone III Design Guidelines1.2Nov 20081 MBAN-466-1.2
AN 465: Implementing OCT Calibration in Stratix III Devices
     Design Example 1 (200 KB)
     Design Example 2 (74 KB)
     Design Example 3 (211 KB)
     Stratix III OCT Power Up Example (46 KB)
1.0Nov 2007623 KBAN-465-1.0
AN 464: DFT/IDFT Reference design1.0Jun 2007187 KBAN-464
AN 463: Using ALTMEMPHY Megafunction with HardCopy II Structured ASICs1.0Jul 2007915 KBAN-463-1.0
Subscribe Alert AN 462: Implementing Multiple Memory Interfaces Using the ALTMEMPHY Megafunction
     Example Design for AN 462: top.qar (715 KB)
1.3Apr 2009784 KBAN-462-1.3
AN458: Alternative Nios II Boot Methods
     AN458 design example files (37 KB)
1.1Sep 2008334 KBAN-458-1.1
AN 457: Integrating Uplink Desubchannelization and Ranging Modules for WiMAX1.0Feb 2007166 KBAN-457-1.0
Subscribe Alert AN 456: PCI Express High Performance Reference Design1.2Aug 2009379 KBAN-456-1.2
AN 455: Understanding CIC Compensation Filters1.0Apr 2007268 KBAN-455-1.0
Subscribe Alert AN 454: Implementing PLL Reconfiguration in Stratix III and Stratix IV Devices
     Design Examples 1 (412 KB)
     Design Examples 2 (236 KB)
2.0Dec 2009868 KBAN-454-2.0
AN 453: HardCopy II Fitting Techniques2.0Nov 2008716 KBAN-453-2.0
AN 452: An OFDM Kernel for WiMAX
     WiMAX OFDMA Reference Design Web Page (8 KB)
1.0Feb 2007319 KBAN-452-1.0
AN 451: Downlink Subchannelization for WiMAX1.0Feb 2007319 KBAN-451-1.0
AN 450: Uplink Desubchannelization for WiMAX1.0Feb 2007319 KBAN-450-1.0
AN 449: External Memory Interface Design Guidelines for Stratix II, Stratix II GX, and Arria GX Devices1.2Sep 2007284 KBAN-449-1.2
AN 448: Stratix III Power Management Design Guide1.3May 2007201 KBAN-448-1.3
Subscribe Alert AN 447: Interfacing Cyclone III and Cyclone IV Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems2.0Nov 2009396 KBAN-447-2.0
AN 446: Debugging Nios II Systems with the SignalTap II Embedded Logic Analyzer
     signal_tap_test software file (4 KB)
1.2Jun 2008257 KBAN-446-1.2
Subscribe Alert AN 445: Design Guidelines for Implementing DDR and DDR2 SDRAM Interfaces in Cyclone III Devices
     AN 445 Design Example (572 KB)
2.2Jun 20092 MBAN-445-2.2
AN 444: Dual DIMM DDR2 SDRAM Interface Design Guidelines1.1May 20097 MBAN-444-1.1
AN 443: External PHY Support in PCI Express MegaCore Functions1.0May 2007435 KBAN-443-1.0
AN 442: Tool Flow for Design of Digital IF for Wireless Systems1.0May 20071 MBAN-442
Subscribe Alert AN 440: Accelerating Nios II Networking Applications
     Accelerating Nios II Networking Applications Design (3 MB)
1.1Jun 2009179 KBAN-440-1.1
AN 439: Constellation Mapper and Demapper for WiMAX1.1May 2007250 KBAN-439-1.1
Subscribe Alert AN 438: Constraining and Analyzing Timing for External Memory Interfaces in Stratix IV, Stratix III, Arria II GX, and Cyclone III Devices
     SIII_phase_shift (5 KB)
4.1May 2009976 KBAN-438-4.1
AN 437: Power Optimization in Stratix III FPGAs2.0Aug 2007219 KBAN-437-2.0
Subscribe Alert AN 436: Using DDR3 SDRAM with Stratix III and Stratix IV Devices
     AN 436 Design Files (11 MB)
4.0Nov 20082 MBAN-436-4.0
Subscribe Alert AN 435: Using DDR and DDR2 SDRAM with Stratix III and Stratix IV Devices
     AN 435 Design Files (3 MB)
2.0Aug 20082 MBAN-435-2.0
AN 434: Channel Estimation & Equalization for Mobile WiMAX Basestations
     Channel Estimation & Equalization Reference Design (8 KB)
1.1May 2007748 KBAN-434-1.1
AN 430: WiMAX OFDMA Ranging1.0Aug 2006769 KBAN-430-1.0
Subscribe Alert AN 429: Remote Configuration Over Ethernet with the Nios II Processor
     Application Note 429 Design Files (3 MB)
2.0Mar 2009207 KBAN-429-2.0
AN 428: MAX II CPLD Design Guidelines1.1Dec 2007425 KBAN-428
Subscribe Alert AN 427: Video and Image Processing Example Design
     Video Processing Reference Design web page (12 KB)
8.0Nov 20093 MBAN-427-8.0
AN 426: Using MAX II CPLDs as Analog Keyboard Encoders1.0Jul 2006308 KBAN-426-1.0
AN 425: Using Command-Line Jam STAPL Solution for Device Programming3.0Jul 2009302 KBAN-425-3.0
AN 424: I/O Simulations Using HSPICE1.0Jun 20062 MBAN-424-1.0
AN 423: Configuring the MicroBlaster Passive Serial Software Driver
     Source Code (149 KB)
1.1Jun 2008211 KBAN-423-1.1
AN 422: Power Management in Portable Systems Using MAX II CPLDs1.0Jul 2006265 KBAN-422-1.0
AN 421: Accelerating WiMAX DUC & DDC System Designs
     WiMAX DUC & DDC Reference Design Web Page (9 KB)
2.2May 2007758 KBAN-421-2.2
AN 418: SRunner: An Embedded Solution for Serial Configuration Device Programming
     Source Code (254 KB)
1.1Jun 2008288 KBAN-418-1.1
AN 417: Accelerating Functions with the C2H Compiler: Scatter-Gather DMA with Checksum
     Scatter-Gather DMA Design Files (6 KB)
1.1Jul 2006424 KBAN-417-1.1
AN 415: DDR and DDR2 SDRAM ECC Reference Design
     ECC Reference Design Files (242 bytes)
1.0Jun 2006291 KBAN-415
AN 414: The JRunner Software Driver: An Embedded Solution for PLD JTAG Configuration
     Source Code (221 KB)
1.0May 2006145 KBAN-414-1.0
AN 413: Using Legacy Integrated Static Data Path and Controller Megafunction with HardCopy II Structured ASICs2.1Jul 2007227 KBAN-413-2.1
AN 412: A Scalable OFDMA Engine for WiMAX
     WiMAX OFDMA Reference Design Web Page
2.1May 2007359 KBAN-412-2.1
AN 411: Understanding PLL Timing for Stratix II Devices
     Design Example 1 (279 KB)
     Design Example 2 (233 KB)
1.0Mar 20061 MBAN-411-1.0
AN 410: MAX II ISP Update with I/O Control & Register Data Retention
     ISP SRAM Download Design Files (11 KB)
1.0Mar 2006126 KBAN-410-1.0
AN 409: Design Example Using the altlvds Megafunction & the External PLL Option in Stratix II Devices
     Design Example (7 MB)
1.0Mar 2006244 KBAN-409-1.0
Subscribe Alert AN 408: DDR2 Memory Interface Termination, Drive Strength, Loading, and Design Layout Guidelines
     SII Simulation Example (3 KB)
     SIII Simulation Example (3 KB)
2.1Jul 20084 MBAN-408-2.1
AN 407: Automotive Audio Reference Design1.0Apr 20062 MBAN-407-1.0
AN 404: FFT/IFFT Block Floating Point Scaling1.0Oct 2005110 KBAN-404-1.0
AN 400: SMBus Interface for the User Flash Memory in MAX II Devices
     SMBus (Read/Write/Erase) Design Files (8 KB)
     SMBus (Read Only) Design Files (8 KB)
1.0Sep 20051 MBAN-400-1.0
AN 398: Using DDR/DDR2 SDRAM With SOPC Builder1.1Aug 2006775 KBAN-398-1.1
AN 396: Crest Factor Reduction1.0Jun 20071 MBAN-396
AN 395: Stratix II Professional FFT Co-Processor Reference Design1.0Aug 2005446 KBAN-395-1.0
AN 393: Stratix II Professional Filtering Lab1.0Aug 20051 MBAN-393-1.0
AN 392: Implementing Multiple Legacy DDR/DDR2 SDRAM Controller Interfaces
     three controller example (26 KB)
     two controller example (15 KB)
2.0Jul 2007306 KBAN-392-2.0
AN 391: Profiling Nios II Systems
     AN 391 Profiler Example Files (15 KB)
1.3Jul 2008406 KBAN-391-1.3
AN 388: High-Performance EMIF Bridge Core1.2Sep 2005435 KBAN-388
AN 387: Upgrading a FIR Compiler v3.1.x Design to v3.2.x1.0May 2005537 KBAN-387-1.0
Subscribe Alert AN 386: Using the Parallel Flash Loader with the Quartus II Software
     Flash Memory (873 bytes)
     Nios Design (567 KB)
5.0Dec 20092 MBAN-386-5.0
AN 385: Using Stratix GX Transceivers for PCI Express1.0Jun 20054 MBAN-385-1.0
AN 384: Using Calibrated Series On-Chip Termination in Stratix II Devices
     User-Mode Calibration Reference Design (Quartus II Version 4.2 SP1) (233 KB)
     User-Mode Calibration Reference Design (Quartus II Version 5.0) (233 KB)
1.0Apr 2005116 KBAN-384-1.0
AN 383: Cyclone II DDR2 SDRAM Demonstration1.0Apr 2005175 KBAN-383-1.0
AN 380: Test DDR or DDR2 SDRAM Interfaces on Hardware Using the Example Driver1.2Jun 2006630 KBAN-380-1.2
AN 379: Active Serial Memory Interface Controller Reference Design
     Design Files (11 KB)
1.0Mar 2005191 KBAN-379-1.0
AN 376: Cyclone II Filtering Lab1.0May 20051 MBAN-376-1.0
AN 375: Cyclone II FFT Co-Processor Reference Design1.0May 2005566 KBAN-375-1.0
AN 373: Avalon Video Input Module1.0Dec 2004154 KBAN-373
AN 372: Avalon LCD Controller1.0Dec 2004159 KBAN-372
AN 371: Automotive Graphics System Reference Design1.0Dec 2004195 KBAN-371
Subscribe Alert AN 370: Using the Serial FlashLoader With the Quartus II Software3.1Apr 20091 MBAN-370-3.1
AN 369: AES3/EBU Reference Design
     AES3/EBU Reference Design Web Page (10 KB)
1.1Feb 20051 MBAN-369
Subscribe Alert AN 367: Implementing PLL Reconfiguration in Stratix II Devices
     Example 1: altpll_reconfig Design with the MIF (244 KB)
     Example 2: altpll_reconfig Design with Write Parameters (249 KB)
     Example 3: altpll_reconfig Design for Phase Shift Stepping (251 KB)
2.1May 2009717 KBAN-367-2.1
AN 366: Understanding I/O Output Timing for Altera Devices1.0Jul 2006311 KBAN-366-1.0
AN 364: Edge Detection Reference Design1.0Oct 20041 MBAN-364-1.0
AN 363: FFT Co-Processor Reference Design1.0Oct 20041 MBAN-363-1.0
AN 362: Stratix II Filtering Lab1.0Oct 20041 MBAN-362-1.0
AN 361: Interfacing DDR & DDR2 SDRAM With Cyclone II Devices1.3Jun 2006380 KBAN-361-1.3
AN 360: Updating Simulation Models for the POS-PHY Level 4 MegaCore Function1.1Dec 200463 KBAN-360-1.1
AN 359: POS-PHY Level 4 MegaCore Function Parameter Selection Calculator
     Parameter Selection Calculator (2 MB)
2.0Sep 2008238 KBAN-359-2.0
Subscribe Alert AN 358: Thermal Management for FPGAs2.0Dec 2009260 KBAN-358-2.0
AN 357: Error Detection & Recovery Using CRC in Altera FPGA Devices1.4Jul 2008371 KBAN-357-1.4
AN 355: Stratix II Device System Power Considerations1.0Jun 2004274 KBAN-355-1.0
Subscribe Alert AN 353: Reflow Soldering Guidelines for Lead-Free Packages2.0Feb 2009155 KBAN-353-2.0
AN 352: FPGA Peripheral Expansion & FPGA Co-Processing1.0Jul 2004552 KBAN352-1.0
AN 351: Simulating Nios II Embedded Processor Designs
     AN 351 Software Files (6 KB)
1.2Nov 2008323 KBAN-351-1.2
AN 350: Upgrading Nios Processor Systems to the Nios II Processor1.1Jul 2006617 KBAN-350-1.1
AN 349: QDR SRAM Controller Reference Design for Stratix & Stratix GX Devices1.0May 2004280 KBAN-349-1.0
AN 348: Interfacing DDR SDRAM with Cyclone Devices1.1Jul 2004441 KBAN-348-1.1
AN 347: Farrow-Based Decimating Sample Rate Converter1.0Mar 2004256 KBAN-347-1.0
AN 346: Using the Nios II Configuration Controller Reference Designs1.2Mar 2009793 KBAN-346-1.2
AN 345: Altera Design Flow for Lattice Semiconductor Users1.1Jan 2005581 KBAN-345-1.1
AN 344: ASI Demonstration2.0Oct 2006145 KBAN-344-2.0
AN 343: OpenCore Evaluation of AMPP Megafunctions1.0Feb 2004294 KBAN-343-1.0
AN 342: Interfacing DDR SDRAM with Stratix & Stratix GX Devices2.0Dec 2005428 KBAN-342-2.0
Subscribe Alert AN 341: Using the Design Security Feature in Stratix II and Stratix II GX Devices2.3Sep 20091 MBAN-341-2.3
Subscribe Alert AN 340: Altera Software Licensing2.3Mar 2009824 KBAN-340-2.3
AN 339: Serial Digital Interface Demonstration for Stratix II GX Devices3.3May 2007288 KBAN-339
AN 336: Using External Series and Parallel Termination with Stratix and Stratix GX Devices1.0Nov 20031 MBAN-336-1.0
AN 335: POS-PHY Level 4 MegaCore Function v2.1.0 Wrapper Features1.0Jan 2004282 KBAN-335-1.0
AN 334: ADI Parallel Port SDRAM Controller Reference Design1.3Jun 2005753 KBAN-334-1.3
AN 333: Developing Peripherals for SOPC Builder
     Slave Peripheral Design Files (455 KB)
     Streaming Slave 1C20 Design Files (1 MB)
     Streaming Slave 1S10 Design Files (1 MB)
     Streaming Slave 1S10ES Design Files (1 MB)
     Streaming Slave 1S40 Design Files (1 MB)
1.0Apr 2004267 KBAN-333-1.0
AN 332: Link-Port Reference Design1.3Feb 20051 MBAN-332
AN 330: Connecting Altera 3.3-V PCI devices to a 5-V PCI Bus1.0Feb 2004112 KBAN-330-1.0
AN 329: ZBT SRAM Controller Reference Design for Stratix & Stratix GX Devices1.0Mar 2004165 KBAN-329-1.0
Subscribe Alert AN 328: Interfacing DDR2 SDRAM with Stratix II, Stratix II GX, and Arria GX Devices
     ALTMEMPHY Example (604 KB)
     Legacy PHY Example (330 KB)
6.0Oct 20093 MBAN-328-6.0
AN 327: Interfacing DDR SDRAM with Stratix II Devices3.2Sep 2008938 KBAN-327-3.2
AN 326: Interfacing QDRII+ & QDRII with Stratix II, Stratix II GX, Stratix, & Stratix GX Devices5.1May 20082 MBAN-326-5.1
AN 325: Interfacing RLDRAM II with Stratix II, Stratix & Stratix GX Devices3.1Nov 20052 MBAN-325-3.1
AN 323: Using SignalTap II Embedded Logic Analyzers in SOPC Builder Systems1.1Nov 2007386 KBAN-323-1.1
AN 322: Porting the Nios GERMS Monitor to Work with Different Flash Memories1.0Sep 2003139 KBAN-322-1.0
AN 320: OpenCore Plus Evaluation of Megafunctions1.6Nov 2007307 KBAN-320-1.6
AN 317: Turbo Encoder Co-processor Reference Design1.2Oct 2003183 KBAN-317-1.2
AN 316: High-Speed Data Interface for Stratix Devices & Fujitsu MB86064 DACs1.0Jul 2003402 KBAN-316-1.0
AN 315: Guidelines for Designing High-Speed FPGA PCBs1.1Feb 20042 MBAN-315-1.1
AN 314: Digital Predistortion Reference Design1.0Jul 20031 MBAN-314
AN 313: Implementing Clock Switchover in Stratix & Stratix GX Devices
     Clock Switchover Example Design (233 KB)
1.0Jan 2004273 KBAN-313-1.0
Subscribe Alert AN 311: ASIC-to-FPGA Design Methodology and Guidelines3.1Apr 2009286 KBAN-311-3.1
AN 308: Building Embedded Processor Systems Using SOPC Builder & Excalibur Devices
     AN 308: Design Files (6 MB)
1.0Mar 20031 MBAN-308-1.0
Subscribe Alert AN 307: Altera Design Flow for Xilinx Users
     an307_DesignExample.zip (4 KB)
6.3Nov 20092 MBAN-307-6.3
AN 306: Implementing Multipliers in FPGA Devices3.0Jul 2004733 KBAN-306-3.0
AN 299: System Development Tools for Excalibur Devices1.1Jun 2003618 KBAN-299-1.1
AN 298: Reconfiguring Excalibur Devices Under Processor Control
     AN 298: Design Files (1 MB)
1.0Feb 2003705 KBAN-298-1.0
AN 294: Crosspoint Switch Matrices in MAX II & MAX 3000A Devices
     16 x 16 Crosspoint Switch (6 KB)
     Customized Crosspoint Switch (7 KB)
2.0Mar 2004205 KBAN-294-2.0
AN 293: Using MAX 7000B Devices to Replace I/O Drivers1.1Nov 2005233 KBAN-293-1.1
AN 287: Using Excalibur DMA Controllers for Video Imaging
     AN 287: Design Files (7 MB)
1.1Feb 2003664 KBAN-287-1.1
AN 286: Implementing LED Drivers in MAX and MAX II Devices2.3Oct 2008164 KBAN-286-2.3
AN 284: Implementing Interrupt Service Routines in Nios Systems
     Example Code (5 KB)
1.0Jan 2003335 KBAN-284-1.0
AN 283: Simulating Altera Devices with IBIS Models1.1Nov 2003166 KBAN-283-1.1
AN 282: Implementing PLL Reconfiguration in Stratix & Stratix GX Devices
     Example 1: Shift Register in LEs (340 KB)
     Example 2: altpll_reconfig Design with the MIF (192 KB)
     Example 3: altpll_reconfig Design (192 KB)
2.0Dec 2005511 KBAN-282-2.0
AN 278: Excalibur Dynamic Reconfiguration with Linux Demonstration
     AN 278: Design Files (17 MB)
2.0Jun 2003811 KBAN-278-2.0
AN 267: Rebuilding the Excalibur Dynamic Reconfiguration with Linux Demonstration1.0Jun 2003318 KBAN-267-1.0
AN 265: Using MAX II & MAX 3000A Devices as a Microcontroller I/O Expander2.0Mar 2004306 KBAN-265-2.0
AN 263: CORDIC Reference Design1.4Jun 2005323 KBAN-263
AN 247: Stratix GX to Mercury Interoperability1.2Jan 200482 KBAN-247-1.2
AN 245: Filtering Reference Design Lab3.0Dec 2004670 KBAN-245-3.0
AN 244: Using Run-From-Flash Mode with the Excalibur Bootloader1.0Sep 2002140 KBAN-244-1.0
AN 242: Excalibur Solutions - Simple Excalibur System
     AN 242: Design Files (468 KB)
1.0Aug 2002245 KBAN-242-1.0
AN 240: Simulating Excalibur Systems1.0Sep 2002335 KBAN-240-1.0
AN 236: Using Source-Synchronous Signaling with DPA in Stratix GX Devices1.1Jan 2003177 KBAN-236-1.1
AN 228: SPI-4.2 Interoperability with PMC-Sierra XENON Family in Stratix GX Devices1.0May 2003633 KBAN-228-1.0
AN 227: SPI-4.2 Interoperability with the Intel IXF1110 in Stratix GX Devices1.0May 2003456 KBAN-227-1.0
Subscribe Alert AN 224: High-Speed Board Layout Guidelines1.2Aug 2009494 KBAN-224-1.2
AN 223: PCI-to-DDR SDRAM Reference Design1.0May 2003507 KBAN-223-1.0
AN 213: Excalibur Remote Reconfiguration Demonstration Design
     AN 213: Design Files (2 MB)
1.0Feb 20032 MBAN-213-1.0
AN 210: Converting Memory from Asynchronous to Synchronous for Stratix & Stratix GX Designs2.0Nov 2002143 KBAN-210-2.0
AN 196: Excalibur Software Debugging Solutions1.2Aug 2002147 KBAN-196-1.2
AN 192: Excalibur Solutions - Embedded Stripe Performance Designs
     AN 192: Design Files (346 KB)
1.2Nov 2002253 KBAN-192-1.2
AN 191: Excalibur Solutions - Using the Interrupt Controller
     AN 191: Design Files (370 KB)
1.3Dec 2002202 KBAN-191-1.3
AN 189: Simulating Nios Embedded Processor Designs2.1Feb 20031 MBAN-189-2.1
AN 188: Custom Instructions for the Nios Embedded Processor1.2Sep 2002313 KBAN-188-1.2
AN 187: Booting Excalibur Devices
     AN 187: Design Files (574 KB)
1.2Mar 2003632 KBAN-187-1.2
AN 186: Using Flexible-LVDS Circuitry in Mercury Devices1.1Nov 2002264 KBAN-186-1.1
AN 185: Thermal Management Using Heat Sinks2.1Mar 2002254 KBA-AN-185-2.1
AN 184: Simultaneous Multi-Mastering with the Avalon Bus1.1Apr 2002135 KBAN-184-1.1
AN 183: ZBT SRAM Controller Reference Design for APEX II Devices1.0Dec 2001211 KBA-AN-183-1.0
AN 181: Excalibur Solutions - Multi-Master Reference Design
     AN 181: Design Files (804 KB)
2.3Nov 2002642 KBAN-181-2.3
AN 180: POS-PHY Level 4-POS-PHY Level 3 Bridge Reference Design1.02Oct 2001545 KBA-AN-180-1.02
AN 179: Designing with ESBs in APEX II Devices1.0Mar 20024 MBA-AN-179-1.0
AN 178: Estimating Nios Resource Usage & Performance1.0Sep 2001224 KBA-AN-178-1.0
AN 177: Excalibur Solutions-Using the Excalibur Stripe PLLs1.3Jul 2002300 KBA-AN-177-1.3
AN 173: Excalibur Solutions - DPRAM Reference Design
     AN 173: Design Files (326 KB)
2.3Aug 2002208 KBA-AN-173-2.3
AN 167: Using Flexible-LVDS I/O Pins in APEX II Devices1.1Aug 2002141 KBA-AN-167-1.1
AN 166: Using High-Speed I/O Standards in APEX II Devices1.May 2003463 KBAN-166-1.8
AN 159: Using HSDI in Source-Synchronous Mode in Mercury Devices1.1Dec 2002246 KBAN-159-1.1
AN 156: Using General-Purpose PLLs with APEX II Devices 1.5Feb 2003431 KBAN-156-1.5
AN 143: Excalibur Solutions - Using the Expansion bus Interface1.0Oct 2002991 KBA-AN143-1.0
AN 142: Excalibur Solutions - Using the Embedded Stripe Bridges 2.1Jun 2002432 KBA-AN142-2.1
AN 141: Excalibur Solutions - Using the SDRAM Controller1.0Sep 2002926 KBA-AN141-1.0
AN 138: LVDS Signaling Using APEX Devices I/O Pins1.0May 2001229 KBA-AN-138-01
AN 134: Using Programmable I/O Standards in Mercury Devices2.1Dec 2002506 KBAN-134-2.1
AN 132: Implementing Multiprotocol Label Switching with Altera PLDs1.0Jan 2001177 KBA-AN-132-01
AN 131: Using General Purpose PLLs in Mercury Devices1.1Oct 2001616 KBA-AN-131-1.1
AN 130: CDR in Mercury Devices1.0Feb 2001225 KBA-AN-130-01
AN 128: Implementing Voice Over Internet Protocol1.1Sep 2000188 KBA-AN-128-01.1
Subscribe Alert AN 120: Using LVDS in APEX 20KE Devices1.5Aug 20091 MBAN-120-1.5
AN 119: Implementing High-Speed Search Applications with Altera CAM
     Source code for fully associative cache (5 KB)
     Source code for direct mapped cache (5 KB)
2.1Jul 20012 MBA-AN-119-2.1
AN 117: Using Selectable I/O Standards in APEX 20KE, APEX 20KC & MAX 7000B Devices2.2Dec 20011 MBA-AN-117-2.2
AN 115: Using the ClockLock & ClockBoost PLL Features in APEX Devices2.6Nov 2003557 KBAN-115-2.6
AN 114: Designing with High-Density BGA Packages for Altera Devices5.1Dec 2007574 KBAN-114-5.1
AN 113: Plastic Package Reliability & Testing1.0Jun 1999180 KBA-AN-133-01
AN 112: Integrating Product-Term Logic in APEX 20K Devices1.0Apr 1999184 KBA-AN-112-01
AN 111: Embedded Programming Using the 8051 and Jam Byte-Code1.2Sep 2008289 KBAN-111-1.2
AN 110: Gate Counting Methodology for APEX 20K Devices1.01Sep 1999169 KBA-AN-110-01.01
AN 109: Using the HP 3070 Tester for In-System Programming1.2Jan 2003123 KBAN-109-1.2
AN 107: Using Altera Devices in Multi-Voltage Systems2.0Aug 2001207 KBA-AN-107-2.0
AN 106: Designing with 2.5-V Devices1.01Jul 1999352 KBA-AN-106-01.01
AN 102: Improving Performance in FLEX 10K Devices with Leonardo Spectrum Software1.0Jun 1999450 KBA-AN-102-01.01
AN 101: Improving Performance in FLEX 10K Devices with the Synplify Software1.0Oct 1998696 KBA-AN-101-01
AN 100: In-System Programmability Guidelines 3.0May 1999217 KBAN-100-3.0
AN 95: In-System Programmability in MAX Devices1.5Sep 2005123 KBAN-095-1.5
AN 94: Understanding MAX 7000 Timing2.0May 1999216 KBA-AN-094-02
AN 92: Understanding FLEX 6000 Timing2.0May 1999244 KBA-AN-107-01
AN 91: Understanding FLEX 10K Timing2.0May 1999301 KBA-AN-091-02
AN 90: SameFrame Pin-Out Design for FineLine BGA Packages1.01Sep 2000277 KBA-AN-090-01.01
AN 83: Binary Numbering Systems1.0Apr 1997174 KBA-AN-083-01
AN 82: Highly Optimized 2-D Convolver1.0Feb 1997285 KBA-AN-082-01
AN 81: Reflow Soldering Guidelines for Surface-Mount Devices4.0Jun 2002147 KBAN-081-04
AN 80: Selecting Sockets for Altera Devices3.0Jan 1999152 KBA-AN-080-03
AN 79: Understanding FLASHlogic Timing1.0Jun 1996311 KBA-AN-079-01
AN 78: Understanding MAX 5000 & Classic Timing3.0May 1999230 KBA-AN-078-03
AN 77: Understanding MAX 9000 Timing3.0May 1999239 KBA-AN-077-03
AN 76: Understanding FLEX 8000 Timing3.0May 1999207 KBA-AN-076-03
AN 75: High-Speed Board Designs4.0Nov 2001768 KBA-AN-75-4.0
AN 74: Evaluating Power for Altera Devices3.1Jul 2001512 KBA-AN-074-03.1
AN 73: Implementing FIR Filters in FLEX Devices1.0Feb 1998205 KBA-AN-073-01.01
AN 71: Guidelines for Handling J-Lead & QFP Devices4.0Jan 1999303 KBA-AN-071-04
AN 51: Using Programmable Logic for Gate Array Designs 1.0Jan 1996303 KBA-AN-051-01
AN 49: Implementing CRCCs in Altera Devices2.1Oct 2005146 KBAN-049-2.1
AN 46: ATM Packet Scheduler in FLEX 8000 Devices 1.0Mar 1995248 KBA-AN-046-01
AN 45: Configuring FLASHlogic Devices1.0Apr 1995159 KBA-AN-045-01
AN 43: Designing for MAX 9000 Devices1.0Aug 1995179 KBA-AN-043-01
AN 39: IEEE 1149.1 (JTAG) Boundary-Scan Testing in Altera Devices6.0Jun 2005360 KBAN-039-6.0
AN 38: Configuring Multiple FLEX 8000 Devices2.01May 1994442 KBA-AN-038-2.01
AN 36: Designing with FLEX 8000 Devices2.0May 1994218 KBA-AN-036-02
AN 33: Configuring FLEX 8000 Devices3.03Jun 2000401 KBA-AN-033-3.03

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