Arria V Device Overview (ver 2013.05.06, May 2013, 675 KB)
Arria V Device Datasheet (ver 3.2, May 2013, 2 MB)
Arria V Device Handbook (18 MB)
Arria V Device Handbook, Volume 1: Device Interfaces and Integration (ver 2013.05.10, May 2013, 3 MB)
Chapter 1. Logic Array Blocks and Adaptive Logic Modules in Arria V Devices (ver 2013.05.06, May 2013, 567 KB) 
- Chapter 2. Embedded Memory Blocks in Arria V Devices (ver 2013.05.06, May 2013, 677 KB)
- Chapter 3. Variable Precision DSP Blocks in Arria V Devices (ver 2013.05.06, May 2013, 718 KB)
- Chapter 4. Clock Networks and PLLs in Arria V Devices (ver 2013.05.06, May 2013, 732 KB)
- Chapter 5. I/O Features in Arria V Devices (ver 2013.05.06, May 2013, 920 KB)
- Chapter 6. High-Speed Differential I/O Interfaces and DPA in Arria V Devices (ver 2013.05.06, May 2013, 819 KB)
- Chapter 7. External Memory Interfaces in Arria V Devices (ver 2013.05.06, May 2013, 882 KB)
- Chapter 8. Configuration, Design Security, and Remote System Upgrades in Arria V Devices (ver 2013.05.10, May 2013, 733 KB)
- Chapter 9. SEU Mitigation for Arria V Devices (ver 2013.05.06, May 2013, 499 KB)
- Chapter 10. JTAG Boundary-Scan Testing in Arria V Devices (ver 2013.05.06, May 2013, 527 KB)
- Chapter 11. Power Management in Arria V Devices (ver 2013.05.06, May 2013, 562 KB)
Section I. Device Core for Arria V Devices
Section II. I/O Interfaces for Arria V Devices
Section III. System Integration for Arria V Devices
Arria V Device Handbook, Volume 2: Transceivers (ver 2013.05.06, May 2013, 3 MB)
- Chapter 1. Transceiver Architecture in Arria V Devices (ver 2013.05.06, May 2013, 1 MB)
- Chapter 2. Transceiver Clocking in Arria V Devices (ver 2013.05.06, May 2013, 818 KB)
- Chapter 3. Transceiver Reset Control and Power Down in Arria V Devices (ver 2013.05.06, May 2013, 569 KB)
- Chapter 4. Transceiver Protocol Configurations in Arria V Devices (ver 2013.05.06, May 2013, 901 KB)
- Chapter 5. Transceiver Custom Configurations in Arria V Devices (ver 2013.05.06, May 2013, 449 KB)
- Chapter 6. Transceiver Configurations in Arria V GZ Devices (ver 2013.05.06, May 2013, 1 MB)
- Chapter 7. Transceiver Loopback Support in Arria V Devices (ver 2013.05.06, May 2013, 474 KB)
- Chapter 8. Dynamic Reconfiguration in Arria V Devices (ver 2013.05.06, May 2013, 508 KB)
Arria V Device Handbook, Volume 3: Hard Processor System Technical Reference Manual (ver 1.3, Nov 2012, 14 MB)
- Chapter 1. Introduction to the Hard Processor System (ver 1.3, Nov 2012, 416 KB)
- Chapter 2. Clock Manager (ver 1.2, Nov 2012, 540 KB)
- Chapter 3. Reset Manager (ver 1.2, Nov 2012, 476 KB)
- Chapter 4. Interconnect (ver 1.2, Nov 2012, 351 KB)
- Chapter 5. HPS-FPGA AXI Bridges (ver 2.0, Nov 2012, 272 KB)
- Chapter 6. Cortex-A9 Microprocessor Unit Subsystem (ver 1.2, Nov 2012, 8 KB)
- Chapter 7. CoreSight Debug and Trace (ver 1.2, Nov 2012, 517 KB)
- Chapter 8. SDRAM Controller Subsystem (ver 1.1, Nov 2012, 511 KB)
- Chapter 9. On-Chip Memory (ver 1.1, Nov 2012, 221 KB)
- Chapter 10. NAND Flash Controller (ver 1.1, Nov 2012, 570 KB)
- Chapter 11. SD/MMC Controller (ver 1.1, Nov 2012, 1 MB)
- Chapter 12. Quad SPI Flash Controller (ver 1.2, Nov 2012, 345 KB)
- Chapter 13. FPGA Manager (ver 1.3, Nov 2012, 244 KB)
- Chapter 14. System Manager (ver 1.2, Nov 2012, 266 KB)
- Chapter 15. Scan Manager (ver 1.2, Nov 2012, 230 KB)
- Chapter 16. DMA Controller (ver 1.1, Nov 2012, 2 MB)
- Chapter 17. Ethernet Media Access Controller (ver 1.2, Nov 2012, 976 KB)
- Chapter 18. USB 2.0 OTG Controller (ver 1.2, Nov 2012, 304 KB)
- Chapter 19. SPI Controller (ver 1.2, Nov 2012, 1 MB)
- Chapter 20. I2C Controller (ver 1.2, Nov 2012, 845 KB)
- Chapter 21. UART Controller (ver 1.2, Nov 2012, 505 KB)
- Chapter 22. General-Purpose I/O Interface (ver 1.2, Nov 2012, 234 KB)
- Chapter 23. Timer (ver 1.2, Nov 2012, 198 KB)
- Chapter 24. Watchdog Timer (ver 1.2, Nov 2012, 270 KB)
- Chapter 25. Introduction to the HPS Component (ver 1.0, Nov 2012, 141 KB)
- Chapter 26. Instantiating the HPS Component (ver 1.1, Nov 2012, 260 KB)
- Chapter 27. HPS Component Interfaces (ver 1.1, Nov 2012, 172 KB)
- Chapter 28. Simulating the HPS Component (ver 1.1, Nov 2012, 275 KB)
- Chapter 1. Booting and Configuration (ver 1.3, Nov 2012, 817 KB)
- Chapter 1. SoC HPS Address Map and Register Definitions, HTML (ver 1.3, Nov 2012, 27 MB)
- Chapter 2. SoC HPS Address Map and Register Definitions, PDF (ver 1.3, May 2013, 13 MB)
Section I. Overview
Section II. System Interconnect
Section III. Cortex-A9 Microprocessor
Section IV. Debug and Trace
Section V. Memory and Memory Controllers
Section VI. Peripherals
Section VII. Hard Processor System User Guide
Section VIII. Appendices
Section IX. SoC HPS Address Map and Register Definitions
Related Documentation
External Memory Interfaces
- Using External Memory Interfaces to Achieve Efficient High-Speed Memory Solutions (ver 1.0, Nov 2011, 589 KB)
Power and Thermal Management
- Arria II and Arria V PowerPlay Early Power Estimator (ver 13.0, May 2013, 7 KB)
PowerPlay Early Power Estimator User Guide (1 MB)
- An Independent Evaluation of Floating-Point DSP Energy Efficiency on Altera 28 nm FPGAs (ver 1.0, Mar 2013, 331 KB)
(BDTI)
- AN657: Thermal Management and Mechanical Handling for Altera TCFCBGA Devices (ver 1.1, Jul 2012, 1 MB)
- Device-Specific Power Delivery Network (PDN) Tool User Guide for Other Supported Device Families (ver 1.0, Dec 2012, 2 MB)
Power Delivery Network (PDN) Tool Version 12.1 for Stratix V, Arria V, Arria II GZ, Cyclone V, and Cyclone IV Devices (4 MB)
- Meeting the Low Power Imperative at 28 nm (ver 2.1, Sep 2012, 1 MB)
- PowerPlay Early Power Estimator User Guide (ver 7.1, Jul 2012, 1 MB)
I/O Interfaces, Protocols and Signal Integrity
- Arria V Hard IP for PCI Express User Guide (ver 1.4, May 2013, 6 MB)
- AN 518: SGMII Interface Implementation Using Soft-CDR Mode of Altera FPGAs (ver 2.1, Dec 2012, 745 KB)
- AN 668: Serial Digital Interface Reference Design for Stratix V GX and Arria V GX Devices (ver 1.0, Sep 2012, 784 KB)
Arria V GX Design Files (2 MB)
Stratix V GX Design Files (1 MB)
- AN653: Implementing the CPRI Protocol using the Deterministic Latency Transceiver PHY IP Core (ver 2013.02.08, Feb 2013, 2 MB)
an653_Reference_Design_File (346 KB)
- Early SSN Estimator User Guide for Altera Programmable Devices (ver 1.0, Nov 2009, 788 KB)
Arria V Early SSN Estimator (528 KB)
Embedded Memory
- Real-Time Challenges and Opportunities in SoCs (ver 1.1, Mar 2013, 1 MB)
DSP
- Altera Product Catalog (ver 12.1, Feb 2013, 2 MB)
- Altera's 28 nm Device Portfolio (ver 2.0, Oct 2012, 1 MB)
Device Configuration and Remote System Upgrades
- Configuration via Protocol (CvP) Implementation in Altera FPGAs User Guide (ver 2013.05.15, May 2013, 2 MB)
user_led.zip (4 KB)
Design Guidelines
- AN 652: Arria V Timing Optimization Guidelines (ver 1.0, Nov 2011, 1 MB)
- Achieving SerDes Interoperability on Altera's 28 nm FPGAs Using Introspect ESP (ver 1.0, Mar 2013, 1 MB)
(Introspect)
- AN 662: Arria V and Cyclone V Design Guidelines (ver 1.0, Jan 2013, 409 KB)
- AN 676: Using the Transceiver Reconfiguration Controller for Dynamic Reconfiguration in Arria V and Cyclone V Devices (ver 2013.04.11, Apr 2013, 912 KB)
AN 676 Reference Design Example (1 MB)
- An Independent Evaluation of Floating-Point DSP Energy Efficiency on Altera 28 nm FPGAs (ver 1.0, Mar 2013, 331 KB)
(BDTI)
- Low-Cost Implementation of High-Performance PCIe Gen2 Hard IP (ver 1.1, Apr 2013, 313 KB)
- Real-Time Challenges and Opportunities in SoCs (ver 1.1, Mar 2013, 1 MB)
- Reducing Development Time for Advanced Medical Endoscopy Systems with an FPGA-Based Approach (ver 1.0, Aug 2012, 669 KB)
- Tips and Techniques for 28-nm Design Optimization (ver 1.0, Nov 2011, 704 KB)
PCB Layout and Packaging
- AN659: Thermal Management and Mechanical Handling for Lidless Flip Chip Ball-Grid Array (ver 1.0, Mar 2012, 980 KB)
(This application note provides guidance on thermal management and mechanical handling of lidless flip chip ball-grid array (FCBGA) for Altera devices. )
- AN657: Thermal Management and Mechanical Handling for Altera TCFCBGA Devices (ver 1.1, Jul 2012, 1 MB)
Development Kits
- Altera Product Catalog (ver 12.1, Feb 2013, 2 MB)
- Arria V GT FPGA Development Board Reference Manual (ver 1.0, Nov 2012, 2 MB)
- Arria V GX FPGA Development Board Reference Manual (ver 1.0, Jul 2012, 2 MB)
- Arria V GT FPGA Development Kit User Guide (ver 1.0, Nov 2012, 2 MB)
- Arria V GX FPGA Development Kit User Guide (ver 1.0, Jul 2012, 2 MB)
- Arria V GX Starter Board Reference Manual (ver 1.2, Mar 2013, 1 MB)
- Arria V GX Starter Kit User Guide (ver 1.2, Mar 2013, 3 MB)
End Applications
- A Validated Methodology for Designing Safe Industrial Systems on a Chip (ver 1.3, Mar 2013, 371 KB)
- Altera's 28 nm Device Portfolio (ver 2.0, Oct 2012, 1 MB)
- Broadcast Design Solutions from Altera (ver 2.0, May 2013, 443 KB)
- Implementing Digital Processing for Automotive Radar Using SoC FPGAs (ver 1.2, Jan 2013, 681 KB)
- Optimize Motor Control Designs with an Integrated FPGA Design Flow (ver 1.2, May 2012, 811 KB)
- Reducing Development Time for Advanced Medical Endoscopy Systems with an FPGA-Based Approach (ver 1.0, Aug 2012, 669 KB)
General Device Documentation
- Altera QAM Design Solution for HD Video (ver 1.0, Nov 2011, 339 KB)
- Altera's User-Customizable ARM-Based SoC FPGAs (ver 1.3, Apr 2013, 1 MB)
- Designing Polyphase DPD Solutions with 28-nm FPGAs (ver 1.0, Jan 2012, 800 KB)
- FPGA-Adaptive Software Debug and Performance Analysis (ver 1.0, May 2013, 717 KB)
- Implementing Digital Processing for Automotive Radar Using SoC FPGAs (ver 1.2, Jan 2013, 681 KB)
- Implementing Efficient Low-Power PCIe Interfaces with Low-Cost FPGAs (ver 1.0, Feb 2013, 466 KB)
- Industrial Motor Drive on a Single FPGA (ver 3.0, Mar 2013, 459 KB)
- Jump-Start Software Development with the SoC FPGA Virtual Target (ver 1.0, Oct 2011, 370 KB)
- Low-Cost Implementation of High-Performance PCIe Gen2 Hard IP (ver 1.1, Apr 2013, 313 KB)
- Optimize Power and Cost with Altera’s Diversified 28-nm Device Portfolio (ver 1.2, Sep 2012, 421 KB)
- Robust Image Format Conversion Solutions (ver 1.0, Nov 2011, 240 KB)
