Literature: Cyclone III Devices

Cyclone III Device Handbook (7 MB)

Cyclone III Device Handbook Volume 1 (ver 3.3, Jan 2010, 6 MB)

Section I. Device Core (1 MB)

Chapter 1. Cyclone III Device Family Overview (ver 2.2, Dec 2009, 244 KB)
Chapter 2. Logic Elements and Logic Array Blocks in Cyclone III Devices (ver 2.2, Dec 2009, 182 KB)
Chapter 3. Memory Blocks in Cyclone III Devices (ver 2.2, Dec 2009, 390 KB)
Chapter 4. Embedded Multipliers in Cyclone III Devices (ver 2.2, Dec 2009, 140 KB)
Chapter 5. Clock Networks and PLLs in Cyclone III Devices (ver 3.2, Dec 2009, 658 KB)

Section II. I/O Interfaces (2 MB)

Chapter 6. Cyclone III Device I/O Features (ver 3.2, Dec 2009, 561 KB)
Chapter 7. High-Speed Differential Interfaces in Cyclone III Devices (ver 3.2, Dec 2009, 515 KB)
Chapter 8. External Memory Interfaces in Cyclone III Devices (ver 2.3, Jan 2010, 300 KB)

Section III. System Integration (2 MB)

Chapter 9. Configuration, Design Security, and Remote System Upgrades in Cyclone III Devices (ver 1.2, Dec 2009, 2 MB)
Chapter 10. Hot-Socketing and Power-On Reset in Cyclone III Devices (ver 3.2, Dec 2009, 124 KB)
Chapter 11. SEU Mitigation in Cyclone III Devices (ver 2.2, Dec 2009, 222 KB)
Chapter 12. IEEE 1149.1 (JTAG) Boundary-Scan Testing for Cyclone III Devices (ver 2.2, Dec 2009, 106 KB)

Cyclone III Device Handbook Volume 2 (ver 3.3, Jan 2010, 1 MB)

Section I. Cyclone III Device Data Sheet (1 MB)

Chapter 1. Cyclone III Device Data Sheet (ver 3.3, Jan 2010, 766 KB)

Cyclone III I/O Timing Spreadsheet

Chapter 2. Cyclone III LS Device Data Sheet (ver 1.2, Dec 2009, 393 KB)

Cyclone III LS I/O Timing Spreadsheet

Related Documentation

External Memory Interfaces

AN 438: Constraining and Analyzing Timing for External Memory Interfaces in Stratix IV, Stratix III, Arria II GX, and Cyclone III Devices (ver 4.1, May 2009, 976 KB)
SIII_phase_shift (5 KB)
AN 445: Design Guidelines for Implementing DDR and DDR2 SDRAM Interfaces in Cyclone III Devices (ver 2.2, Jun 2009, 2 MB)
AN 445 Design Example (572 KB)
AN 462: Implementing Multiple Memory Interfaces Using the ALTMEMPHY Megafunction (ver 1.3, Apr 2009, 784 KB)
Example Design for AN 462: top.qar (715 KB)
External Memory PHY Interface (ALTMEMPHY) (nonAFI) Megafunction User Guide (ver 7.3, Jan 2010, 3 MB)

Power and Thermal Management

Achieving Low Power in 65-nm Cyclone III FPGAs (ver 1.1, Apr 2007, 699 KB)
Cyclone III and Cyclone IV PowerPlay Early Power Estimator (ver 9.1 SP1, Jan 2010, 18 KB)
PowerPlay Early Power Estimator User Guide (600 KB)
PowerPlay Early Power Estimator User Guide (ver 1.1, Jan 2010, 600 KB)

I/O Interfaces, Protocols and Signal Integrity

AN 447: Interfacing Cyclone III and Cyclone IV Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems (ver 2.0, Nov 2009, 396 KB)
AN 479: Design Guidelines for Implementing LVDS Interfaces in Cyclone Series Devices (ver 1.1, Jun 2009, 435 KB)
AN 508: Cyclone III Simultaneous Switching Noise (SSN) Design Guidelines (ver 1.0, Dec 2007, 379 KB)

Embedded Memory

Cyclone_III_Advertorial (ver 1.0, Aug 2008, 846 KB)

DSP

Altera in Portable Entertainment (ver 1.0, May 2007, 226 KB)
Cyclone_III_Advertorial (ver 1.0, Aug 2008, 846 KB)
Altera Product Catalog (ver 7.4, Mar 2010, 3 MB)
Designing military DSP applications (ver 1.0, Apr 2009, 288 KB)
Video and Image Processing Design Using FPGAs (ver 1.1, Mar 2007, 488 KB)

Device Configuration and Remote System Upgrades

AN 478: Using FPGA-Based Parallel Flash Loader with the Quartus II Software (ver 1.0, Nov 2007, 861 KB)
AN 521: Cyclone III Active Parallel Remote System Upgrade Reference Design (ver 1.1, Aug 2009, 994 KB)
AN521 Design Files (1 MB)
AN523: Cyclone III Configuration Interface Guidelines with EPCS Devices (ver 1.1, Jun 2009, 966 KB)

Design Guidelines

AN 466: Cyclone III Design Guidelines (ver 1.2, Nov 2008, 1 MB)
AN523: Cyclone III Configuration Interface Guidelines with EPCS Devices (ver 1.1, Jun 2009, 966 KB)

Development Kits

1080p video framework from Altera (ver 1.0, Apr 2008, 230 KB)
Altera Product Catalog (ver 7.4, Mar 2010, 3 MB)
Cyclone III Development Board Reference Manual (ver 1.4, Mar 2009, 2 MB)
Cyclone III FPGA Starter Board Reference Manual (ver 1.2, Mar 2010, 607 KB)
     Cyclone III Starter Board Schematic (271 KB)
     Cyclone III Starter Board Assembly (3 MB)
     Cyclone III Starter Board BOM (33 KB)
     Cyclone III Starter Board Mechanicals (43 KB)
Cyclone III FPGA Starter Kit User Guide (ver 1.1, Mar 2010, 575 KB)
Cyclone III FPGAs advancing military and aerospace applications (ver 1.0, Oct 2007, 528 KB)
Cyclone III LS FPGA Development Board Reference Manual (ver 1.0, Sep 2009, 1 MB)
Cyclone III LS FPGA Development Kit User Guide (ver 1.0, Sep 2009, 872 KB)
Development boards for broadcast applications (ver 2.0, Apr 2008, 122 KB)
Nios II 3C120 Microprocessor with LCD Controller Data Sheet (ver 1.1, Mar 2009, 634 KB)
Nios II 3C25 Microprocessor with LCD Controller Data Sheet (ver 1.1, Mar 2009, 580 KB)

End Applications

Altera Addresses the SWaP Challenges (ver 1.0, Sep 2007, 149 KB)
Altera Cyclone III FPGAs in Display Applications (ver 1.0, Mar 2007, 126 KB)
Altera Cyclone III FPGAs in Video and Image Processing Applications (ver 2.0, Jun 2009, 176 KB)
Altera Cyclone III FPGAs in Wireless Applications (ver 2.0, Jun 2009, 215 KB)
Altera Enhanced COTS PLD Initiative (ver 1.1, Jul 2008, 122 KB)
Altera in Portable Entertainment (ver 1.0, May 2007, 226 KB)
Automotive-Grade Device Handbook (ver 1.0, Feb 2008, 844 KB)
Cyclone_III_Advertorial (ver 1.0, Aug 2008, 846 KB)
1080p video framework from Altera (ver 1.0, Apr 2008, 230 KB)
A Flexible Architecture to Drive Sharp Two-Way Viewing Angle and Standard LCDs (ver 1.2, Mar 2007, 2 MB)
A Flexible Solution for Industrial Ethernet (ver 2.0, Jul 2009, 852 KB)
Altera in home appliances (ver 1.0, Nov 2008, 135 KB)
Altera in portable entertainment (ver 2.0, Dec 2007, 196 KB)
Broadcast Solutions Supporting Altera's HD Quality Initiative (HDQI) (ver 2.0, Apr 2008, 2 MB)
Broadcast Video Infrastructure Implementation Using FPGAs (ver 1.2, Mar 2007, 596 KB)
Cyclone III FPGAs advancing military and aerospace applications (ver 1.0, Oct 2007, 528 KB)
Designing military DSP applications (ver 1.0, Apr 2009, 288 KB)
Developing MSAN Equipment Using Low-Cost FPGAs (ver 1.1, Jan 2008, 624 KB)
Development boards for broadcast applications (ver 2.0, Apr 2008, 122 KB)
Enabling your core-to-edge applications for net-centric warfare (ver 2.0, Jun 2009, 139 KB)
Energy-Aware Appliance Platform: A New Approach to Home Energy Control (ver 2.0, Jul 2009, 286 KB)
FPGA Run-Time Reconfiguration: Two Approaches (ver 1.0, Mar 2008, 362 KB)
FPGAs Enable Energy-Efficient Motor Control in Next-Generation Smart Home Appliances (ver 1.0, Nov 2008, 309 KB)
Gain Flexibility and Increased Integration With Advanced Cyclone III FPGA PLLs (ver 1.0, Oct 2007, 1 MB)
Generating Panoramic Views by Stitching Multiple Fisheye Images (ver 1.0, May 2009, 779 KB)
Implementing a Cost-Effective Human-Machine Interface for Home Appliances (ver 2.0, Jul 2009, 305 KB)
Industrial market solutions from Altera (ver 3.0, Oct 2007, 530 KB)
Motor control solutions for industrial applications (ver 2.0, Aug 2009, 187 KB)
PARIS platform, an Altera automotive infotainment solution (ver 1.0, Jul 2008, 178 KB)
Protecting the FPGA Design From Common Threats (ver 1.0, Jun 2009, 193 KB)
Satisfying the Demand for Rapid Feature Enhancement in Consumer Display Products (ver 1.0, Mar 2007, 980 KB)
Supporting Unknown FREF Video Applications With PLLs (ver 1.0, Mar 2008, 172 KB)
Unknown FREF Reference Design (931 KB)
Using Cyclone III FPGAs for Clearer LCD HDTV Implementation (ver 1.0, Mar 2007, 214 KB)
Using Cyclone III FPGAs for Emerging Wireless Applications (ver 1.0, Mar 2007, 683 KB)
Using FPGA-Based Channel Bonding for HDTV Over DSL (ver 1.0, Feb 2008, 152 KB)
Using FPGAs to Render Graphics and Drive LCD Interfaces (ver 1.0, Apr 2009, 686 KB)
Video and image processing solutions for military applications (ver 2.0, Jun 2009, 278 KB)
Video Processing on FPGAs for Military Electro-Optical/Infrared Applications (ver 1.0, Mar 2009, 309 KB)
Video Surveillance Implementation Using FPGAs (ver 1.1, Mar 2007, 507 KB)

General Device Documentation

Altera Addresses the SWaP Challenges (ver 1.0, Sep 2007, 149 KB)
Altera Enhanced COTS PLD Initiative (ver 1.1, Jul 2008, 122 KB)
Cyclone III Low-Cost FPGAs (ver 1.0, Mar 2007, 126 KB)
Cyclone III Low-Cost FPGAs (ver 2.0, Apr 2007, 434 KB)
An FPGA Design Security Solution Using a Secure Memory Device (ver 1.0, Oct 2007, 510 KB)
Cyclone III Product Specs (ver 2.0, Mar 2008, 203 KB)
Enabling Design Separation for High-Reliability and Information-Assurance Systems (ver 1.0, Jun 2009, 159 KB)

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