Documentation: Cyclone V Devices

PowerPlay Early Power Estimator

Cyclone V Device Overview (ver 2013.05.06, May 2013, 724 KB)

Cyclone V Device Datasheet (ver 3.4, Jun 2013, 1 MB)

Cyclone V Device Handbook (16 MB)

Cyclone V Device Handbook, Volume 1: Device Interfaces and Integration (ver 2013.06.17, Jun 2013, 3 MB)

Section I. Device Core for Cyclone V Devices

Chapter 1. Logic Array Blocks and Adaptive Logic Modules in Cyclone V Devices (ver 2013.05.06, May 2013, 541 KB)
Chapter 2. Embedded Memory Blocks in Cyclone V Devices (ver 2013.05.06, May 2013, 653 KB)
Chapter 3. Variable-Precision DSP Blocks in Cyclone V Devices (ver 2013.05.06, May 2013, 587 KB)
Chapter 4. Clock Networks and PLLs in Cyclone V Devices (ver 2013.05.06, May 2013, 723 KB)

PLL Connectivity to GCLK and RCLK Networks for Cyclone V Devices

Section II. I/O Interfaces for Cyclone V Devices

Chapter 5. I/O Features in Cyclone V Devices (ver 2013.06.17, Jun 2013, 1 MB)
Chapter 6. External Memory Interfaces in Cyclone V Devices (ver 2013.05.06, May 2013, 853 KB)

Section III. System Integration for Cyclone V Devices

Chapter 7. Configuration, Design Security, and Remote System Upgrades in Cyclone V Devices (ver 2013.06.11, Jun 2013, 724 KB)
Chapter 8. SEU Mitigation for Cyclone V Devices (ver 2013.05.06, May 2013, 499 KB)
Chapter 9. JTAG Boundary-Scan Testing in Cyclone V Devices (ver 2013.05.06, May 2013, 511 KB)
Chapter 10. Power Management in Cyclone V Devices (ver 2013.05.06, May 2013, 546 KB)

Cyclone V Device Handbook, Volume 2: Transceivers (ver 2013.05.06, May 2013, 2 MB)

Chapter 1. Transceiver Architecture in Cyclone V Devices (ver 2013.05.06, May 2013, 887 KB)
Chapter 2. Transceiver Clocking in Cyclone V Devices (ver 2013.05.06, May 2013, 655 KB)
Chapter 3. Transceiver Reset Control and Power Down in Cyclone V Devices (ver 2013.05.06, May 2013, 556 KB)
Chapter 4. Transceiver Protocol Configurations in Cyclone V Devices (ver 2013.05.06, May 2013, 737 KB)
Chapter 5. Transceiver Custom Configurations in Cyclone V Devices (ver 2013.05.06, May 2013, 400 KB)
Chapter 6. Transceiver Loopback Support in Cyclone V Devices (ver 2013.05.06, May 2013, 468 KB)
Chapter 7. Dynamic Reconfiguration in Cyclone V Devices (ver 2013.05.06, May 2013, 496 KB)

Cyclone V Device Handbook, Volume 3: Hard Processor System Technical Reference Manual (ver 1.3, Nov 2012, 14 MB)

Section I. Overview

Chapter 1. Introduction to the Hard Processor System (ver 1.3, Nov 2012, 416 KB)
Chapter 2. Clock Manager (ver 1.2, Nov 2012, 492 KB)
Chapter 3. Reset Manager (ver 1.2, Nov 2012, 470 KB)

Section II. System Interconnect

Chapter 4. Interconnect (ver 1.2, Nov 2012, 304 KB)
Chapter 5. HPS-FPGA AXI Bridges (ver 2.0, Nov 2012, 231 KB)

Section III. Cortex-A9 Microprocessor

Chapter 6. Cortex-A9 Microprocessor Unit Subsystem (ver 1.2, Nov 2012, 474 KB)

Section IV. Debug and Trace

Chapter 7. CoreSight Debug and Trace (ver 1.2, Nov 2012, 465 KB)

Section V. Memory and Memory Controllers

Chapter 8. SDRAM Controller Subsystem (ver 1.1, Nov 2012, 467 KB)
Chapter 9. On-Chip Memory (ver 1.1, Nov 2012, 202 KB)
Chapter 10. NAND Flash Controller (ver 1.1, Nov 2012, 487 KB)
Chapter 11. SD/MMC Controller (ver 1.1, Nov 2012, 1 MB)
Chapter 12. Quad SPI Flash Controller (ver 1.2, Nov 2012, 294 KB)

Section VI. Peripherals

Chapter 13. FPGA Manager (ver 1.3, Nov 2012, 216 KB)
Chapter 14. System Manager (ver 1.2, Nov 2012, 235 KB)
Chapter 15. Scan Manager (ver 1.2, Nov 2012, 206 KB)
Chapter 16. DMA Controller (ver 1.1, Nov 2012, 2 MB)
Chapter 17. Ethernet Media Access Controller (ver 1.2, Nov 2012, 835 KB)
Chapter 18. USB 2.0 OTG Controller (ver 1.2, Nov 2012, 269 KB)
Chapter 19. SPI Controller (ver 1.2, Nov 2012, 1,006 KB)
Chapter 20. I2C Controller (ver 1.2, Nov 2012, 783 KB)
Chapter 21. UART Controller (ver 1.2, Nov 2012, 471 KB)
Chapter 22. General-Purpose I/O Interface (ver 1.2, Nov 2012, 219 KB)
Chapter 23. Timer (ver 1.2, Nov 2012, 179 KB)
Chapter 24. Watchdog Timer (ver 1.2, Nov 2012, 245 KB)
Chapter 25. CAN Controller (ver 1.2, Nov 2012, 355 KB)

Section VII. Hard Processor System User Guide

Chapter 26. Introduction to the HPS Component (ver 1.0, Nov 2012, 125 KB)
Chapter 27. Instantiating the HPS Component (ver 1.1, Nov 2012, 260 KB)
Chapter 28. HPS Component Interfaces (ver 1.1, Nov 2012, 173 KB)
Chapter 29. Simulating the HPS Component (ver 1.1, Nov 2012, 275 KB)

Section VIII. Appendices

Chapter 1. Booting and Configuration (ver 1.3, Nov 2012, 806 KB)

Section IX. SoC HPS Address Map and Register Definitions

Chapter 1. SoC HPS Address Map and Register Definitions (ver 1.3, Nov 2012, 27 MB)
Chapter 2. SoC HPS Address Map and Register Definitions, PDF (ver 1.3, May 2013, 13 MB)

Related Documentation

Power and Thermal Management

Achieving Lowest System Power with Low-Power 28-nm FPGAs (ver 1.0, Mar 2012, 467 KB)
Device-Specific Power Delivery Network (PDN) Tool User Guide for Arria II/Stratix IV/Stratix III Device Families (ver 1.1, Dec 2012, 1 MB)
     Power Delivery Network (PDN) Tool for Arria II GX Devices (2 MB)
     Power Deliver Network (PDN) Tool for Stratix IV Devices (2 MB)
     Power Delivery Network (PDN) Tool for Stratix III Devices (2 MB)
Device-Specific Power Delivery Network (PDN) Tool User Guide for Stratix V, Arria V, Arria II GZ, Cyclone V, and Cyclone IV Device Families (ver 1.0, Dec 2012, 2 MB)
Power Delivery Network (PDN) Tool Version 12.1 for Stratix V, Arria V, Arria II GZ, Cyclone V, and Cyclone IV Devices (4 MB)
PowerPlay Early Power Estimator User Guide (ver 8.0, Jun 2013, 1 MB)

I/O Interfaces, Protocols and Signal Integrity

Cyclone V Hard IP for PCI Express User Guide (ver 1.4, May 2013, 6 MB)
AN653: Implementing the CPRI Protocol using the Deterministic Latency Transceiver PHY IP Core (ver 2013.02.08, Feb 2013, 2 MB)
an653_Reference_Design_File (346 KB)

Embedded Memory

Increasing Efficiency with Hard Memory Controllers in Low-Cost 28 nm FPGAs (ver 1.1, Nov 2012, 577 KB)

DSP

Altera Product Catalog (ver 13.0, Jun 2013, 2 MB)
Altera's 28 nm Device Portfolio (ver 2.0, Oct 2012, 1 MB)

Device Configuration and Remote System Upgrades

Configuration via Protocol (CvP) Implementation in Altera FPGAs User Guide (ver 2013.05.15, May 2013, 2 MB)
user_led.zip (4 KB)

Design Guidelines

AN 662: Arria V and Cyclone V Design Guidelines (ver 1.0, Jan 2013, 409 KB)
AN 676: Using the Transceiver Reconfiguration Controller for Dynamic Reconfiguration in Arria V and Cyclone V Devices (ver 2013.04.11, Apr 2013, 912 KB)
AN 676 Reference Design Example (1 MB)
Low-Cost Implementation of High-Performance PCIe Gen2 Hard IP (ver 1.1, Apr 2013, 313 KB)
Reducing Development Time for Advanced Medical Endoscopy Systems with an FPGA-Based Approach (ver 1.0, Aug 2012, 669 KB)
Tips and Techniques for 28-nm Design Optimization (ver 1.0, Nov 2011, 704 KB)

PCB Layout and Packaging

AN659: Thermal Management and Mechanical Handling for Lidless Flip Chip Ball-Grid Array (ver 1.0, Mar 2012, 980 KB)
(This application note provides guidance on thermal management and mechanical handling of lidless flip chip ball-grid array (FCBGA) for Altera devices. )

Development Kits

Altera Product Catalog (ver 13.0, Jun 2013, 2 MB)
Cyclone V E FPGA Development Board Reference Manual (ver 1.0, Nov 2012, 1 MB)
Cyclone V E FPGA Development Kit User Guide (ver 1.0, Nov 2012, 2 MB)
Cyclone V GT FPGA Development Kit User Guide (ver 1.0, May 2013, 2 MB)
Cyclone V GX FPGA Development Board Reference Manual (ver 1.2, May 2013, 1 MB)
Cyclone V GX FPGA Development Kit User Guide (ver 1.1, Oct 2012, 3 MB)
Cyclone V SoC Development Board Reference Manual (ver 1.0, May 2013, 2 MB)
Cyclone V SoC Development Kit User Guide (ver 1.0, May 2013, 2 MB)

End Applications

Driving Innovative Industrial Solutions (ver 1006-1.0, May 2013, 2 MB)
A Validated Methodology for Designing Safe Industrial Systems on a Chip (ver 1.3, Mar 2013, 371 KB)
Altera's 28 nm Device Portfolio (ver 2.0, Oct 2012, 1 MB)
Broadcast Design Solutions from Altera (ver 2.0, May 2013, 443 KB)
Broadcast video and image processing (ver 2.1, Mar 2012, 411 KB)
Displays (ver 2.0, Mar 2012, 257 KB)
Optimize Motor Control Designs with an Integrated FPGA Design Flow (ver 1.2, May 2012, 811 KB)
Overcoming Smart Grid Equipment Design Challenges with FPGAs (ver 1.0, Feb 2013, 1 MB)
Reducing Development Time for Advanced Medical Endoscopy Systems with an FPGA-Based Approach (ver 1.0, Aug 2012, 669 KB)

General Device Documentation

Achieving Lowest System Power with Low-Power 28-nm FPGAs (ver 1.0, Mar 2012, 467 KB)
Altera's User-Customizable ARM-Based SoC (ver 1.3, Apr 2013, 1 MB)
Cyclone V FPGAs (ver 1.3, May 2013, 460 KB)
FPGA-Adaptive Software Debug and Performance Analysis (ver 1.0, May 2013, 717 KB)
Implementing Efficient Low-Power PCIe Interfaces with Low-Cost FPGAs (ver 1.0, Feb 2013, 466 KB)
Industrial Motor Drive on a Single FPGA (ver 3.0, Mar 2013, 459 KB)
Jump-Start Software Development with the SoC FPGA Virtual Target (ver 1.0, Oct 2011, 370 KB)
Low-Cost Implementation of High-Performance PCIe Gen2 Hard IP (ver 1.1, Apr 2013, 313 KB)
Reducing Total System Cost with Low-Power 28-nm FPGAs (ver 1.1, Apr 2012, 517 KB)

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