HardCopy II Device Handbook (3 MB)
HardCopy II Device Handbook, Volume 1 (ver 4.5, Sep 2008, 3 MB)
HardCopy II Device Handbook, Volume 2 (ver 4.5, Sep 2008, 285 KB)
Related Documentation
External Memory Interfaces
- AN 328: Interfacing DDR2 SDRAM with Stratix II, Stratix II GX, and Arria GX Devices (ver 6.0, Oct 2009, 3 MB)
ALTMEMPHY Example (604 KB)
Legacy PHY Example (330 KB)
- AN 413: Using Legacy Integrated Static Data Path and Controller Megafunction with HardCopy II Structured ASICs (ver 2.1, Jul 2007, 227 KB)
- AN 463: Using ALTMEMPHY Megafunction with HardCopy II Structured ASICs (ver 1.0, Jul 2007, 915 KB)
- AN 550: Using the DLL Phase Offset Feature in Stratix FPGAs and HardCopy ASICs (ver 2.0, Mar 2010, 547 KB)
altmemphy_ext_dll.zip (48 KB)
altmemphy_int_dll.zip (47 KB)
static_dll.zip (18 KB)
- DDR Timing Wizard User Guide (ver 3.0, Nov 2007, 2 MB)
- External Memory PHY Interface (ALTMEMPHY) (nonAFI) Megafunction User Guide (ver 7.3, Jan 2010, 3 MB)
Power and Thermal Management
- Stratix II, Stratix II GX, and HardCopy II PowerPlay Early Power Estimator (ver 8.1, Nov 2008, 2 MB)
PowerPlay Early Power User Guide for Stratix II, Stratix II GX, and HardCopy II (0 bytes)
- TB 097: HardCopy II Military Temperature Range Support (ver 1.0, Sep 2007, 190 KB)
I/O Interfaces, Protocols and Signal Integrity
- AN 477: Designing RGMII Interface with FPGA and HardCopy Devices (ver 2.0, Jan 2010, 519 KB)
- Input Signal Edge Rate Guidance (ver 1.0, Jun 2005, 63 KB)
DSP
- Altera Product Catalog (ver 7.4, Mar 2010, 3 MB)
Design Guidelines
- AN 432: Using Different PLL Settings Between Stratix II and HardCopy II Devices (ver 1.2, Mar 2010, 149 KB)
- AN 311: ASIC-to-FPGA Design Methodology and Guidelines (ver 3.1, Apr 2009, 286 KB)
- AN 453: HardCopy II Fitting Techniques (ver 2.0, Nov 2008, 716 KB)
- AN 477: Designing RGMII Interface with FPGA and HardCopy Devices (ver 2.0, Jan 2010, 519 KB)
- AN 536: Design Guidelines for Preparing HardCopy II ASICs (ver 1.0, Sep 2008, 1 MB)
- HardCopy II Clock Uncertainty Calculator User Guide (ver 1.0, Aug 2007, 611 KB)
HCII_Clock_Uncertainty_Calculator.zip (1,005 KB)
Development Kits
- Altera Product Catalog (ver 7.4, Mar 2010, 3 MB)
End Applications
- Altera Addresses the SWaP Challenges (ver 1.0, Sep 2007, 149 KB)
- Altera Enhanced COTS PLD Initiative (ver 1.1, Jul 2008, 122 KB)
- Altera FPGAs for radar and advanced sensors (ver 1.0, Oct 2007, 219 KB)
- Broadband access solutions from Altera (ver 1.0, Sep 2007, 263 KB)
General Device Documentation
- Altera Addresses the SWaP Challenges (ver 1.0, Sep 2007, 149 KB)
- Altera Enhanced COTS PLD Initiative (ver 1.1, Jul 2008, 122 KB)
- Altera FPGAs for radar and advanced sensors (ver 1.0, Oct 2007, 219 KB)
- Broadband access solutions from Altera (ver 1.0, Sep 2007, 263 KB)
- Generating Functionally Equivalent FPGAs and ASICs With a Single Set of RTL and Synthesis/Timing Constraints (ver 1.2, Feb 2009, 459 KB)
- HardCopy II ASIC Family Errata Sheet (ver 1.1, Dec 2008, 74 KB)
- HardCopy Structured ASIC (ver 1.0, Feb 2006, 1 MB)
