Literature: HardCopy IV Devices

HardCopy IV Device Handbook (11 MB)

HardCopy IV Device Handbook, Volume 1 (ver 2.2, Jan 2010, 3 MB)

Section I. Device Core (345 KB)

Chapter 1. HardCopy IV Device Family Overview (ver 2.2, Jan 2010, 224 KB)
Chapter 2. Logic Array Block and Adaptive Logic Module Implementation in HardCopy IV Devices (ver 1.0, Dec 2008, 98 KB)
Chapter 3. DSP Block Implementation in HardCopy IV Devices (ver 1.0, Dec 2008, 118 KB)
Chapter 4. TriMatrix Embedded Memory Blocks in HardCopy IV Devices (ver 2.1, Jan 2010, 84 KB)
Chapter 5. Clock Networks and PLLs in HardCopy IV Devices (ver 2.1, Jan 2010, 133 KB)

Section II. I/O Interfaces (780 KB)

Chapter 6. HardCopy IV Device I/O Features (ver 2.1, Jan 2010, 260 KB)
Chapter 7. External Memory Interfaces in HardCopy IV Devices (ver 2.1, Jan 2010, 455 KB)
Chapter 8. High-Speed Differential I/O Interfaces and DPA in HardCopy IV Devices (ver 2.1, Jan 2010, 388 KB)

Section III. Hot Socketing and Testing (123 KB)

Chapter 9. Hot Socketing and Power On-Reset in HardCopy IV Devices (ver 1.0, Dec 2008, 209 KB)
Chapter 10. IEEE 1149.1 (JTAG) Boundary Scan Testing in HardCopy IV Devices (ver 2.0, Jun 2009, 84 KB)

Section IV. Power and Thermal Management (123 KB)

Chapter 11. Power Supply and Temperature Sensing Diode in HardCopy IV Devices (ver 1.1, Jan 2010, 134 KB)

HardCopy IV Device Handbook, Volume 2 (ver 2.1, Jan 2010, 2 MB)

Section I. HardCopy IV Design Flow and Prototyping with Stratix IV Devices (1 MB)

Chapter 1. HardCopy IV Design Flow Using the Quartus II Software (ver 2.1, Jan 2010, 744 KB)
Chapter 2. HardCopy Design Center Implementation Process (ver 1.0, Dec 2008, 171 KB)
Chapter 3. Mapping Stratix IV Device Resources to HardCopy IV Devices (ver 2.1, Jan 2010, 409 KB)
Chapter 4. Matching Stratix IV Power and Configuration Requirements with HardCopy IV Devices (ver 2.0, Jun 2009, 449 KB)

HardCopy IV Device Handbook, Volume 3 (ver 1.0, Jun 2009, 8 MB)

Section I. Transceiver Architecture (9 MB)

Chapter 1. HardCopy IV GX Transceiver Architecture (ver 1.0, Jun 2009, 5 MB)
Chapter 2. HardCopy IV GX Dynamic Reconfiguration (ver 1.0, Jun 2009, 4 MB)
Chapter 3. HardCopy IV GX ALTGX_RECONFIG Megafunction User Guide (ver 1.0, Jun 2009, 240 KB)

HardCopy IV Device Handbook, Volume 4 (ver 1.0, Jun 2009, 532 KB)

Section I. HardCopy IV Device Datasheet (458 KB)

Chapter 1. DC and Switching Characteristics of HardCopy IV Devices (ver 1.0, Jun 2009, 449 KB)

Related Documentation

External Memory Interfaces

AN 550: Using the DLL Phase Offset Feature in Stratix FPGAs and HardCopy ASICs (ver 2.0, Mar 2010, 547 KB)
     altmemphy_ext_dll.zip (48 KB)
     altmemphy_int_dll.zip (47 KB)
     static_dll.zip (18 KB)
External Memory PHY Interface (ALTMEMPHY) (nonAFI) Megafunction User Guide (ver 7.3, Jan 2010, 3 MB)

Power and Thermal Management

Altera at 40 nm: Jitter-, Signal Integrity-, Power-, and Process-Optimized Transceivers (ver 1.0, May 2008, 3 MB)
PowerPlay Early Power Estimator User Guide (ver 1.1, Jan 2010, 600 KB)
Stratix III, Stratix IV, HardCopy III and HardCopy IV PowerPlay Early Power Estimator (ver 9.1 SP1, Jan 2010, 7 KB)
PowerPlay Early Power Estimator User Guide For Stratix III and Stratix IV FPGAs (600 KB)

I/O Interfaces, Protocols and Signal Integrity

Altera at 40 nm: Jitter-, Signal Integrity-, Power-, and Process-Optimized Transceivers (ver 1.0, May 2008, 3 MB)
AN 477: Designing RGMII Interface with FPGA and HardCopy Devices (ver 2.0, Jan 2010, 519 KB)
Input Signal Edge Rate Guidance (ver 1.0, Jun 2005, 63 KB)
PCI Express hard intellectual property solutions from Altera (ver 2.0, Jul 2009, 165 KB)

DSP

40-nm Stratix IV FPGAs and HardCopy IV ASICs (ver 1.1, Sep 2008, 372 KB)
Altera Product Catalog (ver 7.4, Mar 2010, 3 MB)
Designing military DSP applications (ver 1.0, Apr 2009, 288 KB)

Design Guidelines

AN 311: ASIC-to-FPGA Design Methodology and Guidelines (ver 3.1, Apr 2009, 286 KB)
AN 477: Designing RGMII Interface with FPGA and HardCopy Devices (ver 2.0, Jan 2010, 519 KB)

Development Kits

Altera Product Catalog (ver 7.4, Mar 2010, 3 MB)
Broadcast design solutions from Altera (ver 1.0, Feb 2009, 156 KB)

End Applications

Altera Addresses the SWaP Challenges (ver 1.0, Sep 2007, 149 KB)
Altera Enhanced COTS PLD Initiative (ver 1.1, Jul 2008, 122 KB)
Broadband access solutions from Altera (ver 1.0, Sep 2007, 263 KB)
Broadcast design solutions from Altera (ver 1.0, Feb 2009, 156 KB)
Designing base transceiver station (BTS) channel cards with transceiver FPGAs and ASICs (ver 1.0, Feb 2009, 141 KB)
Designing military DSP applications (ver 1.0, Apr 2009, 288 KB)
Designing remote radio head applications with transceiver FPGAs (ver 1.0, Feb 2009, 164 KB)
DO-254-certifiable IP cores (ver 2.0, Nov 2008, 119 KB)
Enabling your core-to-edge applications for net-centric warfare (ver 2.0, Jun 2009, 139 KB)
FPGA companion chip solutions from Altera (ver 1.0, Nov 2009, 283 KB)
GPON solutions from Altera (ver 2.0, Feb 2009, 143 KB)
HardCopy ASICs (ver 1.1, Jul 2008, 277 KB)
HardCopy IV ASICs for military applications (ver 2.0, Mar 2009, 238 KB)
PARIS platform, an Altera automotive infotainment solution (ver 1.0, Jul 2008, 178 KB)

General Device Documentation

40-nm Stratix IV FPGAs and HardCopy IV ASICs (ver 1.1, Sep 2008, 372 KB)
Altera Addresses the SWaP Challenges (ver 1.0, Sep 2007, 149 KB)
Altera Enhanced COTS PLD Initiative (ver 1.1, Jul 2008, 122 KB)
Altera at 40 nm: Jitter-, Signal Integrity-, Power-, and Process-Optimized Transceivers (ver 1.0, May 2008, 3 MB)
Broadband access solutions from Altera (ver 1.0, Sep 2007, 263 KB)
Generating Functionally Equivalent FPGAs and ASICs With a Single Set of RTL and Synthesis/Timing Constraints (ver 1.2, Feb 2009, 459 KB)
HardCopy ASICs (ver 1.1, Jul 2008, 277 KB)
Leveraging the 40-nm Process Node to Deliver the World's Most Advanced Custom Logic Devices (ver 1.1, Feb 2009, 377 KB)

Please give us feedback