Literature: Nios II Processor

These handbooks serve as the primary documentation for the Nios^® II processor.

The Nios II Processor Reference Handbook answers the question “What is the Nios II processor?” and is the primary reference for the Nios II processor architecture.
The Nios II Software Developer’s Handbook answers the question “How do I write programs for the Nios II processor?” and is the primary reference for programming the Nios II processor.
The Quartus^® II Development Software Handbook, Volume 5: Embedded Peripherals describes peripherals provided by Altera that work seamlessly with the Nios II processor and are included with Quartus II software.

Other related documents, such as tutorials and user guides, cover specific topics that are not included in the handbooks.

Embedded Documentation One-Click Download

The files provide a snapshot of the Nios II processor, the Nios II C-to-Hardware (C2H) acceleration compiler, SOPC Builder, and embedded peripherals documentation. After extracting the files, refer to the documentation.htm file for a list of included documents.

Additional Documentation

Nios II Performance Benchmarks
Nios II Design Contest Papers
Nios II Hardware Development
Software Development
C-to-Hardware (C2H) Acceleration Compiler
Development Tools, Kits, and Boards
SOPC Builder System Development
Using Megafunctions
Other Related Documentation

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Nios II Processor Reference Handbook (ver 9.1, Nov 2009, 2 MB)

Section I. Nios II Processor Design (993 KB)

Chapter 1. Introduction (ver 9.1.0, Nov 2009, 135 KB)
Chapter 2. Processor Architecture (ver 9.1.0, Nov 2009, 272 KB)
Chapter 3. Programming Model (ver 9.1.0, Nov 2009, 439 KB)
Chapter 4. Instantiating the Nios II Processor in SOPC Builder (ver 9.1.0, Nov 2009, 333 KB)

Section II. Nios II Processor Implementation and Reference (628 KB)

Chapter 5. Nios II Core Implementation Details (ver 9.1.0, Nov 2009, 265 KB)
Chapter 6. Nios II Processor Revision History (ver 9.1.0, Nov 2009, 87 KB)
Chapter 7. Application Binary Interface (ver 9.1.0, Nov 2009, 119 KB)
Chapter 8. Instruction Set Reference (ver 9.1.0, Nov 2009, 420 KB)

Nios II Software Developer's Handbook (ver 9.1, Nov 2009, 2 MB)

Section I. Nios II Software Development (546 KB)

Chapter 1. Overview (ver 9.0.0, Mar 2009, 222 KB)
Chapter 2. Getting Started with the Graphical User Interface (ver 9.1.0, Nov 2009, 166 KB)
Chapter 3. Getting Started from the Command Line (ver 9.1.0, Nov 2009, 120 KB)
Chapter 4. Nios II Software Build Tools (ver 9.1.0, Nov 2009, 334 KB)

Section II. Hardware Abstraction Layer (519 KB)

Chapter 5. Overview of the Hardware Abstraction Layer (ver 9.1.0, Nov 2009, 90 KB)
Chapter 6. Developing Programs Using the Hardware Abstraction Layer (ver 9.1.0, Nov 2009, 317 KB)
Chapter 7. Developing Device Drivers for the Hardware Abstraction Layer (ver 9.1.0, Nov 2009, 231 KB)

Section III. Advanced Programming Topics (454 KB)

Chapter 8. Exception Handling (ver 9.1.0, Nov 2009, 275 KB)
Chapter 9. Cache and Tightly-Coupled Memory (ver 9.1.0, Nov 2009, 89 KB)
Chapter 10. MicroC/OS-II Real Time Operating System (ver 9.1.0, Nov 2009, 95 KB)
Chapter 11. Ethernet and the NicheStack TCP/IP Stack - Nios II Edition (ver 9.1.0, Nov 2009, 112 KB)
Chapter 12. Read-Only Zip File System (ver 9.1.0, Nov 2009, 62 KB)
Chapter 13. Publishing Component Information to Embedded Software (ver 9.1.0, Nov 2009, 92 KB)

Section IV. Reference Material (831 KB)

Chapter 14. HAL API Reference (ver 9.1.0, Nov 2009, 308 KB)
Chapter 15. Nios II Software Build Tools Reference (ver 9.1.0, Nov 2009, 467 KB)

Appendix A. Using the Nios II Integrated Development Environment (ver 9.1.0, Nov 2009, 178 KB)

Volume 4: SOPC Builder (ver 9.1, Nov 2009, 1 MB)

Section I. SOPC Builder Features (745 KB)

Chapter 1. Introduction to SOPC Builder (ver 9.1.0, Nov 2009, 176 KB)
Chapter 2. System Interconnect Fabric for Memory-Mapped Interfaces (ver 9.1.0, Nov 2009, 239 KB)
Chapter 3. System Interconnect Fabric for Streaming Interfaces (ver 9.1.0, Nov 2009, 121 KB)
Chapter 4. SOPC Builder Components (ver 9.1.0, Nov 2009, 186 KB)
Chapter 5. Using SOPC Builder with the Quartus II Software (ver 9.1.0, Nov 2009, 127 KB)
Chapter 6. Component Editor (ver 9.1.0, Nov 2009, 122 KB)
Chapter 7. Component Interface Tcl Reference (ver 9.1.0, Nov 2009, 279 KB)
Chapter 8. Archiving SOPC Builder Projects (ver 9.1.0, Nov 2009, 77 KB)

Section II. Building Systems with SOPC Builder (410 KB)

Chapter 9. SOPC Builder Memory Subsystem Development Walkthrough (ver 9.1.0, Nov 2009, 327 KB)
Chapter 10. SOPC Builder Component Development Walkthrough (ver 9.1.0, Nov 2009, 153 KB)

Altera Avalon Checksum

Section III. Interconnect Components (479 KB)

Chapter 11. Avalon Memory-Mapped Bridges (ver 9.1.0, Nov 2009, 415 KB)
Chapter 12. Avalon Streaming Interconnect Components (ver 9.1.0, Nov 2009, 127 KB)

Volume 5: Embedded Peripherals (ver 9.1.1, Feb 2010, 3 MB)

Section I. Off-Chip Interface Peripherals (2 MB)

Chapter 1. SDRAM Controller Core (ver 9.1.0, Nov 2009, 187 KB)
Chapter 2. CompactFlash Core (ver 9.1.0, Nov 2009, 80 KB)
Chapter 3. Common Flash Interface Controller Core (ver 9.1.0, Nov 2009, 108 KB)
Chapter 4. EPCS Device Controller Core (ver 9.1.0, Nov 2009, 86 KB)
Chapter 5. JTAG UART Core (ver 9.1.0, Nov 2009, 161 KB)
Chapter 6. UART Core (ver 9.1.0, Nov 2009, 177 KB)
Chapter 7. SPI Core (ver 9.1.0, Nov 2009, 144 KB)
Chapter 8. Optrex 16207 LCD Controller Core (ver 9.0.0, Nov 2009, 73 KB)
Chapter 9. PIO Core (ver 9.1.0, Nov 2009, 98 KB)
Chapter 10. Avalon-ST Serial Peripheral Interface Core (ver 9.1.0, Nov 2009, 175 KB)
Chapter 11. PCI Lite Core (ver 9.1.0, Nov 2009, 269 KB)
Chapter 12. Cyclone III Remote Update Controller Core (ver 9.1.0, Nov 2009, 113 KB)

Section II. On-Chip Storage Peripherals (2 MB)

Chapter 13. Avalon-ST Single Clock and Dual Clock FIFO Cores (ver 9.1.0, Nov 2009, 170 KB)
Chapter 14. On-Chip FIFO Memory Core (ver 9.1.0, Nov 2009, 141 KB)
Chapter 15. Avalon-ST Multi-Channel Shared Memory FIFO Core (ver 9.1.0, Nov 2009, 167 KB)

Section III. Transport and Communication (775 KB)

Chapter 16. SPI Slave/JTAG to Avalon Master Bridge Cores (ver 9.1.0, Nov 2009, 191 KB)
Chapter 17. Avalon Streaming Channel Multiplexer and Demultiplexer Cores (ver 9.1.0, Nov 2009, 92 KB)
Chapter 18. Avalon-ST Bytes to Packets and Packets to Bytes Converter Cores (ver 9.1.0, Nov 2009, 143 KB)
Chapter 19. Avalon Packets to Transactions Converter Core (ver 9.1.0, Nov 2009, 110 KB)
Chapter 20. Avalon-ST Round Robin Scheduler Core (ver 9.1.0, Nov 2009, 106 KB)

Section IV. Peripherals (870 KB)

Chapter 23. Scatter-Gather DMA Controller Core (ver 9.1.0, Nov 2009, 177 KB)
Chapter 24. DMA Controller Core (ver 9.1.0, Nov 2009, 129 KB)
Chapter 25. Video Sync Generator and Pixel Converter Cores (ver 9.1.0, Nov 2009, 130 KB)
Chapter 26. Interval Timer Core (ver 9.1.0, Mar 2009, 144 KB)
Chapter 27. Vectored Interrupt Controller Core (ver 9.1.0, Nov 2009, 313 KB)
Chapter 28. Mutex Core (ver 9.1.0, Nov 2009, 77 KB)
Chapter 29. Mailbox Core (ver 9.1.0, Nov 2009, 83 KB)

Section V. Test and Debug Peripherals (610 KB)

Chapter 30. Avalon-ST JTAG Interface Core (ver 9.1.0, Nov 2009, 123 KB)
Chapter 31. System ID Core (ver 9.1.0, Nov 2009, 70 KB)
Chapter 32. Performance Counter Core (ver 91.0, Nov 2009, 108 KB)
Chapter 33. Avalon Streaming Test Pattern Generator and Checker Cores (ver 9.1.0, Nov 2009, 236 KB)

Section VI. Clock Control Peripherals (334 KB)

Chapter 35. PLL Cores (ver 9.1.0, Nov 2009, 119 KB)

Embedded Design Handbook (ver 2.5, Dec 2009, 2 MB)

Section I. Introduction (293 KB)

Chapter 1. First-Time Designer's Guide (ver 2.1, Jan 2009, 293 KB)

Section II. Nios II Software Development (1 MB)

Chapter 2. Developing Nios II Software (ver 1.3, Dec 2009, 630 KB)
Chapter 3. Debugging Nios II Designs (ver 1.3, Dec 2009, 480 KB)
Chapter 4. Nios II Command-Line Tools (ver 2.1, Apr 2009, 152 KB)
Chapter 5. Optimizing Nios II C2H Compiler Results (ver 1.1, Jun 2008, 468 KB)

edh_c2h_optimization_design_files.zip

Section III. System Level Design (1 MB)

Chapter 6. Avalon Memory-Mapped Design Optimizations (ver 1.1, Jun 2008, 332 KB)
Chapter 7. Memory System Design (ver 1.1, Jun 2008, 198 KB)
Chapter 8. Hardware Acceleration and Coprocessing (ver 1.1, Jun 2008, 163 KB)
Chapter 9. Verification and Board Bring-Up (ver 1.2, Nov 2008, 240 KB)
Chapter 10. Interfacing an External Processor to an Altera FPGA (ver 1.0, Feb 2009, 549 KB)