For a general introduction to features and design flow in the Quartus II software, see the Introduction to Quartus II Manual (PDF).
Please take our 1-minute survey to give us your feedback.
Quartus II Help
Quartus II Handbook v9.1 (Complete Five-Volume Set) (28 MB)
Volume 1: Design and Synthesis (ver 9.1.1, Dec 2009, 7 MB)
Chapter 1. Design Planning with the Quartus II Software (ver 9.1.0, Nov 2009, 197 KB) - Chapter 2. Quartus II Incremental Compilation for Hierarchical and Team-Based Design (ver 9.1.0, Nov 2009, 799 KB)
- Chapter 3. Quartus II Design Flow for MAX+PLUS II Users (ver 9.1.0, Nov 2009, 1 MB)
- Chapter 4. Quartus II Support for HardCopy Series Devices (ver 9.1.0, Nov 2009, 805 KB)
- Chapter 5. Design Recommendations for Altera Devices and the Quartus II Design Assistant (ver 9.1.0, Nov 2009, 498 KB)
- Chapter 6. Recommended HDL Coding Styles (ver 9.1.0, Nov 2009, 588 KB)
- Chapter 7. Managing Metastability with the Quartus II Software (ver 9.1.0, Nov 2009, 199 KB)
- Chapter 8. Best Practices for Incremental Compilation Partitions and Floorplan Assignments (ver 9.1.0, Nov 2009, 743 KB)
- Chapter 9. Quartus II Integrated Synthesis (ver 9.1.1, Dec 2009, 568 KB)
- Chapter 10. Synopsys Synplify Support (ver 9.1.0, Nov 2009, 401 KB)
- Chapter 11. Mentor Graphics Precision Synthesis Support (ver 9.1.0, Nov 2009, 443 KB)
- Chapter 12. Mentor Graphics LeonardoSpectrum Support (ver 9.1.0, Nov 2009, 224 KB)
- Chapter 13. Analyzing Designs with Quartus II Netlist Viewers (ver 9.1.0, Nov 2009, 1 MB)
Section I. Design Flows (3 MB)
Section II. Design Guidelines (2 MB)
Section III. Synthesis (3 MB)
Volume 2: Design Implementation and Optimization (ver 9.1, Nov 2009, 10 MB)
- Chapter 1. Assignment Editor (ver 9.1.0, Nov 2009, 187 KB)
- Chapter 2. Command-Line Scripting (ver 9.1.0, Nov 2009, 328 KB)
- Chapter 3. Tcl Scripting (ver 9.1.0, Nov 2009, 3 MB)
- Chapter 4. Managing Quartus II Projects (ver 9.1.0, Nov 2009, 887 KB)
- Chapter 5. I/O Management (ver 9.1.0, Nov 2009, 913 KB)
- Chapter 6. Simultaneous Switching Noise (SSN) Analysis and Optimizations (ver 9.1.0, Nov 2009, 595 KB)
- Chapter 7. Signal Integrity with Third-Party Tools (ver 9.1.0, Nov 2009, 415 KB)
- Chapter 8. Mentor Graphics PCB Design Tools Support (ver 9.1.0, Nov 2009, 727 KB)
- Chapter 9. Cadence PCB Design Tools Support (ver 9.1.0, Nov 2009, 508 KB)
- Chapter 10. Area and Timing Optimization (ver 9.1.0, Nov 2009, 781 KB)
- Chapter 11. Power Optimization (ver 9.1.0, Nov 2009, 620 KB)
- Chapter 12. Analyzing and Optimizing the Design Floorplan (ver 9.1.0, Nov 2009, 1 MB)
- Chapter 13. Netlist Optimizations and Physical Synthesis (ver 9.1.0, Nov 2009, 221 KB)
- Chapter 14. Design Space Explorer (ver 9.1.0, Nov 2009, 169 KB)
- Chapter 15. Engineering Change Management with the Chip Planner (ver 9.1.0, Nov 2009, 501 KB)
Section I. Scripting and Constraint Entry (4 MB)
Section II. I/O and PCB Tools (3 MB)
Section III. Area, Timing and Power Optimization (3 MB)
Section IV. Engineering Change Management (2 MB)
Volume 3: Verification (ver 9.1, Nov 2009, 7 MB)
- Chapter 1. Quartus II Simulator (ver 9.1.0, Nov 2009, 340 KB)
- Chapter 2. Simulating Designs with EDA Tools (ver 9.1.0, Nov 2009, 314 KB)
- Chapter 3. Mentor Graphics ModelSim Support (ver 9.1.0, Nov 2009, 498 KB)
- Chapter 4. Synopsys VCS and VCS-MX Support (ver 9.1.0, Nov 2009, 508 KB)
- Chapter 5. Cadence NC-Sim Support (ver 9.1.0, Nov 2009, 453 KB)
- Chapter 6. Aldec Active-HDL Support (ver 9.1.0, Nov 2009, 367 KB)
- Chapter 7. Simulating Altera IP in Third-Party Simulation Tools (ver 9.1.0, Nov 2009, 116 KB)
- Chapter 8. The Quartus II TimeQuest Timing Analyzer (ver 9.1.0, Nov 2009, 1 MB)
- Chapter 9. Best Practices for the Quartus II TimeQuest Timing Analyzer (ver 9.1.0, Nov 2009, 192 KB)
- Chapter 10. Switching to the Quartus II TimeQuest Timing Analyzer (ver 9.1.0, Nov 2009, 381 KB)
- Chapter 11. Quartus II Classic Timing Analyzer (ver 9.1.0, Nov 2009, 412 KB)
- Chapter 12. Synopsys PrimeTime Support (ver 9.1.0, Nov 2009, 304 KB)
- Chapter 13. PowerPlay Power Analysis (ver 9.1.0, Nov 2009, 310 KB)
- Chapter 14. Quick Design Debugging Using SignalProbe (ver 9.1.0, Nov 2009, 313 KB)
- Chapter 15. Design Debugging Using the SignalTap II Embedded Logic Analyzer (ver 9.1.0, Nov 2009, 1 MB)
- Chapter 16. In-System Debugging Using External Logic Analyzers (ver 9.1.0, Nov 2009, 220 KB)
- Chapter 17. In-System Updating of Memory and Constants (ver 9.1.0, Nov 2009, 257 KB)
- Chapter 18. Design Debugging Using In-System Sources and Probes (ver 9.1.0, Nov 2009, 213 KB)
- Chapter 19. Cadence Encounter Conformal Support (ver 9.1.0, Nov 2009, 362 KB)
- Chapter 20. Quartus II Programmer (ver 9.1.0, Nov 2009, 886 KB)
Section I. Simulation (2 MB)
Section II. Timing Analysis (2 MB)
Section III. Power Estimation and Analysis (639 KB)
Section IV. In-System Design Debugging (691 KB)
Section V. Formal Verification (1 MB)
Section VI. Device Programming (1 MB)
Volume 4: SOPC Builder (ver 9.1, Nov 2009, 1 MB)
- Chapter 1. Introduction to SOPC Builder (ver 9.1.0, Nov 2009, 176 KB)
- Chapter 2. System Interconnect Fabric for Memory-Mapped Interfaces (ver 9.1.0, Nov 2009, 239 KB)
- Chapter 3. System Interconnect Fabric for Streaming Interfaces (ver 9.1.0, Nov 2009, 121 KB)
- Chapter 4. SOPC Builder Components (ver 9.1.0, Nov 2009, 186 KB)
- Chapter 5. Using SOPC Builder with the Quartus II Software (ver 9.1.0, Nov 2009, 127 KB)
- Chapter 6. Component Editor (ver 9.1.0, Nov 2009, 122 KB)
- Chapter 7. Component Interface Tcl Reference (ver 9.1.0, Nov 2009, 279 KB)
- Chapter 8. Archiving SOPC Builder Projects (ver 9.1.0, Nov 2009, 77 KB)
- Chapter 9. SOPC Builder Memory Subsystem Development Walkthrough (ver 9.1.0, Nov 2009, 327 KB)
- Chapter 10. SOPC Builder Component Development Walkthrough (ver 9.1.0, Nov 2009, 153 KB)
- Chapter 11. Avalon Memory-Mapped Bridges (ver 9.1.0, Nov 2009, 415 KB)
- Chapter 12. Avalon Streaming Interconnect Components (ver 9.1.0, Nov 2009, 127 KB)
Section I. SOPC Builder Features (745 KB)
Section II. Building Systems with SOPC Builder (410 KB)
Section III. Interconnect Components (479 KB)
Volume 5: Embedded Peripherals (ver 9.1.1, Feb 2010, 3 MB)
- Chapter 1. SDRAM Controller Core (ver 9.1.0, Nov 2009, 187 KB)
- Chapter 2. CompactFlash Core (ver 9.1.0, Nov 2009, 80 KB)
- Chapter 3. Common Flash Interface Controller Core (ver 9.1.0, Nov 2009, 108 KB)
- Chapter 4. EPCS Device Controller Core (ver 9.1.0, Nov 2009, 86 KB)
- Chapter 5. JTAG UART Core (ver 9.1.0, Nov 2009, 161 KB)
- Chapter 6. UART Core (ver 9.1.0, Nov 2009, 177 KB)
- Chapter 7. SPI Core (ver 9.1.0, Nov 2009, 144 KB)
- Chapter 8. Optrex 16207 LCD Controller Core (ver 9.0.0, Nov 2009, 73 KB)
- Chapter 9. PIO Core (ver 9.1.0, Nov 2009, 98 KB)
- Chapter 10. Avalon-ST Serial Peripheral Interface Core (ver 9.1.0, Nov 2009, 175 KB)
- Chapter 11. PCI Lite Core (ver 9.1.0, Nov 2009, 269 KB)
- Chapter 12. Cyclone III Remote Update Controller Core (ver 9.1.0, Nov 2009, 113 KB)
- Chapter 13. Avalon-ST Single Clock and Dual Clock FIFO Cores (ver 9.1.0, Nov 2009, 170 KB)
- Chapter 14. On-Chip FIFO Memory Core (ver 9.1.0, Nov 2009, 141 KB)
- Chapter 15. Avalon-ST Multi-Channel Shared Memory FIFO Core (ver 9.1.0, Nov 2009, 167 KB)
- Chapter 16. SPI Slave/JTAG to Avalon Master Bridge Cores (ver 9.1.0, Nov 2009, 191 KB)
- Chapter 17. Avalon Streaming Channel Multiplexer and Demultiplexer Cores (ver 9.1.0, Nov 2009, 92 KB)
- Chapter 18. Avalon-ST Bytes to Packets and Packets to Bytes Converter Cores (ver 9.1.0, Nov 2009, 143 KB)
- Chapter 19. Avalon Packets to Transactions Converter Core (ver 9.1.0, Nov 2009, 110 KB)
- Chapter 20. Avalon-ST Round Robin Scheduler Core (ver 9.1.0, Nov 2009, 106 KB)
- Chapter 21. Avalon-ST Delay Core (ver 9.1.1, Feb 2010, 119 KB)
- Chapter 22. Avalon-ST Splitter Core (ver 9.1.1, Feb 2010, 122 KB)
- Chapter 23. Scatter-Gather DMA Controller Core (ver 9.1.0, Nov 2009, 177 KB)
- Chapter 24. DMA Controller Core (ver 9.1.0, Nov 2009, 129 KB)
- Chapter 25. Video Sync Generator and Pixel Converter Cores (ver 9.1.0, Nov 2009, 130 KB)
- Chapter 26. Interval Timer Core (ver 9.1.0, Mar 2009, 144 KB)
- Chapter 27. Vectored Interrupt Controller Core (ver 9.1.0, Nov 2009, 313 KB)
- Chapter 28. Mutex Core (ver 9.1.0, Nov 2009, 77 KB)
- Chapter 29. Mailbox Core (ver 9.1.0, Nov 2009, 83 KB)
- Chapter 30. Avalon-ST JTAG Interface Core (ver 9.1.0, Nov 2009, 123 KB)
- Chapter 31. System ID Core (ver 9.1.0, Nov 2009, 70 KB)
- Chapter 32. Performance Counter Core (ver 91.0, Nov 2009, 108 KB)
- Chapter 33. Avalon Streaming Test Pattern Generator and Checker Cores (ver 9.1.0, Nov 2009, 236 KB)
- Chapter 34. Avalon Streaming Data Pattern Generator and Checker Cores (ver 9.1.1, Feb 2010, 203 KB)
- Chapter 35. PLL Cores (ver 9.1.0, Nov 2009, 119 KB)
Section I. Off-Chip Interface Peripherals (2 MB)
Section II. On-Chip Storage Peripherals (2 MB)
Section III. Transport and Communication (775 KB)
Section IV. Peripherals (870 KB)
Section V. Test and Debug Peripherals (610 KB)
Section VI. Clock Control Peripherals (334 KB)
Related Documentation
Release Notes
- Quartus II Software version 9.1, SP1 Device Support Release Notes (ver 1.0, Jan 2010, 82 KB)
- Quartus II Software version 9.1 Release Notes (ver 1.0, Nov 2009, 142 KB)
Getting Started
- Megafunction Overview User Guide (ver 1.0, Feb 2009, 329 KB)
- Introduction to the Quartus II Software (ver 9.1, Nov 2009, 4 MB)
- Quartus II Quick Start Guide (ver 7.2, Oct 2007, 537 KB)
Installation and Licensing
- Altera Software Installation and Licensing (ver 9.1, Nov 2009, 2 MB)
- AN 340: Altera Software Licensing (ver 2.3, Mar 2009, 824 KB)
QSF Settings, SDC, and Tcl Scripting Reference Manuals
- Quartus II Settings File Reference Manual (ver 7.0, Dec 2009, 7 MB)
- Quartus II Scripting Reference Manual (ver 9.1, Dec 2009, 3 MB)
- SDC and TimeQuest API Reference Manual (ver 5.0, Dec 2009, 847 KB)
Design Guidelines and Applications
- AN 433: Constraining and Analyzing Source-Synchronous Interfaces (ver 2.1, Nov 2009, 1 MB)
- AN 567: Quartus II Design Separation Flow (ver 1.0, Jun 2009, 3 MB)
- AN 519: Stratix IV Design Guidelines (ver 1.1, May 2009, 493 KB)
- AN 370: Using the Serial FlashLoader With the Quartus II Software (ver 3.1, Apr 2009, 1 MB)
- Quartus II TimeQuest Timing Analyzer Cookbook (ver 1.0, Aug 2008, 482 KB)
- AN 481: Applying Multicycle Exceptions in the TimeQuest Timing Analyzer (ver 1.0, Jul 2008, 2 MB)
- Understanding Metastability in FPGAs (ver 1.2, Jul 2009, 584 KB)
- AN 438: Constraining and Analyzing Timing for External Memory Interfaces in Stratix IV, Stratix III, Arria II GX, and Cyclone III Devices (ver 4.1, May 2009, 976 KB)
SIII_phase_shift (5 KB)
- AN 563: Arria II GX Design Guidelines (ver 1.0, Feb 2009, 752 KB)
- AN 466: Cyclone III Design Guidelines (ver 1.2, Nov 2008, 1 MB)
- Advanced Synthesis Cookbook: A Design Guide for Stratix II, Stratix III, and Stratix IV Devices (ver 5.0, Jul 2008, 2 MB)
Advanced Synthesis Cookbook Design Files (4 MB)
- AN 469: Stratix III Design Guidelines (ver 1.1, May 2008, 628 KB)
- AN 474: Implementing Stratix III Programmable I/O Delay Settings in the Quartus II Software (ver 1.2, Mar 2008, 365 KB)
- AN 428: MAX II CPLD Design Guidelines (ver 1.1, Dec 2007, 425 KB)
- Designing With Low-Level Primitives User Guide (ver 3.0, Mar 2007, 492 KB)
- AN 411: Understanding PLL Timing for Stratix II Devices (ver 1.0, Mar 2006, 1 MB)
Design Example 1 (279 KB)
Design Example 2 (233 KB)
Benchmarking and Design Migration Techniques
- AN 307: Altera Design Flow for Xilinx Users (ver 6.3, Nov 2009, 2 MB)
an307_DesignExample.zip (4 KB)
- AN 311: ASIC-to-FPGA Design Methodology and Guidelines (ver 3.1, Apr 2009, 286 KB)
- Comparing IP Integration Approaches for FPGA Implementation (ver 1.1, Feb 2008, 195 KB)
- Performing Equivalent Timing Analysis Between Altera TimeQuest and Xilinx Trace (ver 1.0, Nov 2007, 1 MB)
- FPGA Performance Benchmarking Methodology (ver 1.6, Aug 2007, 246 KB)
- AN 345: Altera Design Flow for Lattice Semiconductor Users (ver 1.1, Jan 2005, 581 KB)
- TB 84: Differences in Logic Utilization between Quartus II & Synplify Report Files (ver 1.0, Nov 2002, 107 KB)
SOPC Builder System Development
- Avalon Interface Specifications (ver 1.2, Apr 2009, 485 KB)
(Replaces "Avalon Memory-Mapped Interface Specification" and "Avalon Streaming Interface Specification")
- AN 346: Using the Nios II Configuration Controller Reference Designs (ver 1.2, Mar 2009, 793 KB)
- AN458: Alternative Nios II Boot Methods (ver 1.1, Sep 2008, 334 KB)
AN458 design example files (37 KB)
- Comparing IP Integration Approaches for FPGA Implementation (ver 1.1, Feb 2008, 195 KB)
- AN 323: Using SignalTap II Embedded Logic Analyzers in SOPC Builder Systems (ver 1.1, Nov 2007, 386 KB)
- AN 398: Using DDR/DDR2 SDRAM With SOPC Builder (ver 1.1, Aug 2006, 775 KB)
Using Megafunctions
- Integer Arithmetic Megafunctions User Guide (ver 1.0, Nov 2009, 2 MB)
altaccumulate_DesignExample.zip (90 KB)
altecc_DesignExample1.zip (79 KB)
altecc_DesignExample2.zip (115 KB)
altmemmult_DesignExample.zip (186 KB)
altmult_accum_DesignExample.zip (105 KB)
altmult_add_DesignExample.zip (77 KB)
altmult_complex_DesignExample.zip (156 KB)
altsqrt_DesignExample.zip (198 KB)
parallel_adder_DesignExample.zip (97 KB)
- Floating-Point Megafunctions User Guide (ver 2.0, Nov 2009, 2 MB)
Design Examples and ModelSim Files (36 MB) - Viterbi Compiler User Guide (ver 9.1, Nov 2009, 991 KB)
- NCO MegaCore Function User Guide (ver 9.1, Nov 2009, 968 KB)
- FFT MegaCore Function User Guide (ver 9.1, Nov 2009, 1 MB)
- CIC MegaCore Function User Guide (ver 9.1, Nov 2009, 780 KB)
- Reed-Solomon Compiler User Guide (ver 9.1, Nov 2009, 642 KB)
- Automating DSP Simulation and Implementation of Military Sensor Systems (ver 1.0, Mar 2009, 373 KB)
- ALTDLL and ALTDQ_DQS Megafunctions User Guide (ver 2.0, Dec 2008, 5 MB)
ALTDLL_ALTDQ_DQS_DesignExample_ex1 (796 KB)
ALTDLL_ALTDQ_DQS_ex1_msim (397 KB)
- Phase-Locked Loops Reconfiguration Megafunction User Guide (ALTPLL_RECONFIG) (ver 4.0, Jul 2008, 7 MB)
altpll_reconfig_DesignExample1_ex1.zip (167 KB)
altpll_reconfig_DesignExample_ex2.zip (189 KB)
altpll_reconfig_DesignExample_ex3.zip (316 KB)
altpll_reconfig_ex1_msim.zip (68 KB)
altpll_reconfig_ex2_msim.zip (68 KB)
altpll_reconfig_ex3_msim.zip (432 KB)
- Thermal Sensor (ALTTEMP_SENSE) Megafunction User Guide (ver 2.0, Feb 2010, 223 KB)
alttemp_sense_ex1.zip (11 KB)
- External Memory PHY Interface (ALTMEMPHY) (nonAFI) Megafunction User Guide (ver 7.3, Jan 2010, 3 MB)
- ALTLVDS Megafunction User Guide (ver 6.1, Nov 2009, 966 KB)
altlvds_DesignExample.zip (203 KB)
altlvds_DesignExample_ex2.zip (113 KB)
altlvds_DesignExample_ex3.zip (252 KB)
altlvds_DesignExample_ex4.zip (31 KB)
altlvds_DesignExample_ex5.zip (12 KB)
altlvds_ex1_msim.zip (92 KB)
altlvds_ex2_msim.zip (58 KB)
altlvds_ex3_msim.zip (104 KB)
altlvds_ex4_msim.zip (433 KB)
- Phase-Locked Loop Megafunction User Guide (ALTPLL) (ver 8.0, Nov 2009, 806 KB)
ddr_clk.zip (98 KB)
ddr-clk-msim.zip (6 KB)
shift_clk.zip (387 KB)
shift_clk_msim.zip (10 KB)
- ALTDQ and ALTDQS Megafunction User Guides (ver 3.1, Nov 2009, 642 KB)
altdq_dqs_DesignExample.zip (67 KB)
altdq_dqs_msim.zip (11 KB)
- Active Serial Memory Interface Megafunction User Guide (ALTASMI_PARALLEL) (ver 3.0, Sep 2009, 395 KB)
- Remote Update Circuitry Megafunction User Guide (ALTREMOTE_UPDATE) (ver 2.4, Apr 2009, 928 KB)
altremote_update Design Example 1 (16 KB)
altremote_update Design Example 2 (16 KB)
altremote_update ModelSim Design Example 1 (12 KB)
altremote_update ModelSim Design Example 2 (12 KB)
- I/O Buffer Megafunction (ALTIOBUF) User Guide (ver 2.0, Dec 2008, 1 MB)
altiobuf_design_example_1.zip (56 KB)
altiobuf_ex1_msim.zip (91 KB)
- Double Data Rate I/O Megafunction User Guide (ALTDDIO_IN, ALTDDIO_OUT, and ALTDDIO_BIDIR) (ver 4.2, Jun 2007, 4 MB)
altddio_DesignExample_ex1.zip (112 KB)
altddio_DesignExample_ex2.zip (140 KB)
altddio_ex1_msim.zip (18 KB)
altddio_ex2_msim.zip (17 KB)
- Clock Control Block Megafunction User Guide (ALTCLKCTRL) (ver 2.4, Apr 2007, 337 KB)
altclkctrl Design Example (104 KB)
altclkctrl Design Example ModelSim (5 KB)
- Dynamic Calibrated On-Chip Termination Megafunction User Guide (ALTOCT) (ver 2.0, Dec 2006, 268 KB)
alt_oct_msim.zip (30 KB)
altoct_DesignExample.zip (30 KB)
- Flash Memory Megafunction User Guide (ver 2.0, Jul 2006, 1 MB)
alt_ufm Archive Files (72 KB)
alt_ufm ModelSim Files (16 KB) - DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP User Guide (ver 1.1, Nov 2009, 2 MB)
- DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Gui (ver 1.1, Nov 2009, 3 MB)
- HyperTransport MegaCore Function User Guide (ver 9.1, Nov 2009, 738 KB)
- ASI MegaCore Function User Guide (ver 9.1, Nov 2009, 363 KB)
- DDR and DDR2 SDRAM Controller Compiler User Guide (ver 9.0, Mar 2009, 2 MB)
- AN 386: Using the Parallel Flash Loader with the Quartus II Software (ver 5.0, Dec 2009, 2 MB)
Flash Memory (873 bytes)
Nios Design (567 KB)
- AN 370: Using the Serial FlashLoader With the Quartus II Software (ver 3.1, Apr 2009, 1 MB)
- Virtual JTAG (sld_virtual_jtag) Megafunction User Guide (ver 2.0, Dec 2008, 1 MB)
sld_virtual_jtag - Design Example 1 (140 KB)
sld_virtual_jtag - Design Example 2 (304 KB) - SCFIFO and DCFIFO Megafunctions User Guide (ver 6.1, Jan 2010, 395 KB)
DCFIFO Design Example (33 KB)
- Shift Register (RAM-Based) Megafunction User Guide (ALTSHIFT_TAPS) (ver 2.0, Jul 2008, 438 KB)
DE_altshift_taps.zip (5 KB)
- RAM Initializer Megafunction User Guide (ALTMEM_INIT) (ver 1.0, May 2008, 524 KB)
DE1_internalROM.zip (8 KB)
DE2_externalROM.zip (10 KB)
- One-Time Programmable (ALTOTP) Megafunction User Guide (ver 1.0, Nov 2009, 243 KB)
DesignExample_otpfuse.zip (22 KB)
- Internal Memory (RAM and ROM) User Guide (ver 1.0, Nov 2009, 884 KB)
Internal_Memory_DesignExample.zip (33 KB)
- Shift Register Megafunction User Guide (LPM_SHIFTREG) (ver 3.0, Jan 2007, 939 KB)
lpm_shiftreg Design Files Archive Example 1 (84 KB)
lpm_shiftreg Design Files Example 1 (80 KB)
lpm_shiftreg Design Files Archive Example 2 (75 KB)
lpm_shiftreg Design Files Example 2 (70 KB)
lpm_shiftreg ModelSim Files Example 1 (5 KB)
lpm_shiftreg ModelSim Files Example 2 (4 KB)
- Flash Memory Megafunction User Guide (ver 2.0, Jul 2006, 1 MB)
alt_ufm Archive Files (72 KB)
alt_ufm ModelSim Files (16 KB)
- First-In-First-Out Partitioner Megafunction User Guide (FIFO Partitioner) (ver 1.2, Aug 2005, 306 KB)
Arithmetic
DSP
I/O
Interfaces
JTAG-accessible Extensions
Memory Compiler
Programming Hardware
- USB Blaster Download Cable User Guide (ver 2.5, Apr 2009, 500 KB)
- EthernetBlaster Communications Cable User Guide (ver 1.1, Jul 2008, 1 MB)
- ByteBlaster II Download Cable User Guide (ver 1.4, Jul 2008, 295 KB)
- MasterBlaster Serial/USB Communications Cable User Guide (ver 1.1, Jul 2008, 222 KB)
- ByteBlasterMV Download Cable User Guide (ver 1.0, Aug 2004, 400 KB)
Other Related Documentation
- AN 433: Constraining and Analyzing Source-Synchronous Interfaces (ver 2.1, Nov 2009, 1 MB)
- AN 370: Using the Serial FlashLoader With the Quartus II Software (ver 3.1, Apr 2009, 1 MB)
- Video and image processing solutions for military applications (ver 2.0, Jun 2009, 278 KB)
- AN 453: HardCopy II Fitting Techniques (ver 2.0, Nov 2008, 716 KB)
- AN 549: Managing Designs with Multiple FPGAs (ver 1.0, Sep 2008, 776 KB)
- Increasing Productivity With Quartus II Incremental Compilation (ver 1.0, May 2008, 169 KB)
- FPGA Power Management and Modeling Techniques (ver 1.0, Nov 2007, 696 KB)
- AN 437: Power Optimization in Stratix III FPGAs (ver 2.0, Aug 2007, 219 KB)
