Literature: Stratix GX Device Handbook
The Stratix® GX Device Handbook is composed of three volumes. Volume 1 is the Stratix GX FPGA family data sheet. Volume 2 provides detailed information on the device features, including the transceiver. Volume 3 contains information on configuration, remote system upgrades, and Stratix GX board design guidelines. To view all three volumes, click the link below.
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Volume 1 (ver 1.2, Jun 2006, 2,788 KB)
Section I.
Stratix GX Device Family Data Sheet (2,691 KB)
- Chapter 1. Introduction to the Stratix GX Device Data Sheet (ver 1.0, Feb 2005, 495 KB)
- Chapter 2. Stratix GX Transceivers (ver 1.1, Jun 2006, 349 KB)
- Chapter 3. Source-Synchronous Signaling with DPA (ver 1.1, Aug 2005, 216 KB)
- Chapter 4. Stratix GX Architecture (ver 1.0, Feb 2005, 1,284 KB)
- Chapter 5. Configuration & Testing (ver 1.0, Feb 2005, 499 KB)
- Chapter 6. DC & Switching Characteristics (ver 1.2, Jun 2006, 1,157 KB)
- Chapter 7. Reference & Ordering Information (ver 1.0, Feb 2005, 433 KB)
Volume 2 (ver 2.0, Jun 2006, 9,849 KB)
Section I.
Stratix GX Transceiver User Guide (6,199 KB)
- Chapter 1. Introduction (ver 1.2, Jun 2006, 116 KB)
- Chapter 2. Stratix GX Analog Description (ver 1.2, Jun 2006, 553 KB)
- Chapter 3. Custom Mode (ver 1.2, Jun 2006, 949 KB)
- Chapter 4. SONET Mode (ver 1.2, Jun 2006, 800 KB)
- Chapter 5. XAUI Mode (ver 1.2, Jun 2006, 917 KB)
- Chapter 6. GIGE Mode (ver 1.2, Jun 2006, 787 KB)
- Chapter 7. Loopback Modes (ver 1.2, Jun 2006, 67 KB)
- Chapter 8. Stratix GX Built-In Self Test (BIST) (ver 1.1, Aug 2005, 1,624 KB)
- Chapter 9. Reset Control & Power Down (ver 1.0, Feb 2005, 661 KB)
- Chapter 10. Data & Control Codes (ver 1.0, Feb 2005, 485 KB)
- Chapter 11. Ports & Parameters (ver 1.1, Jun 2006, 137 KB)
- Chapter 12. REFCLKB Pin Constraints (ver 1.0, Feb 2005, 561 KB)
Section II.
Clock Management (1,471 KB)
Section III.
Memory (518 KB)
Section IV.
I/O Standards (869 KB)
Section V.
Digital Signal Processing (940 KB)
Volume 3 (ver 1.2, Jun 2006, 4,844 KB)
Section I.
Configuration & Remote System Upgrades (1,157 KB)
Section II.
Design Guidelines (2,584 KB)
Related Documentation
Data Sheets
User Guides
- Double Data Rate I/O Megafunction User Guide (ALTDDIO_IN, ALTDDIO_OUT, and ALTDDIO_BIDIR) (ver 4.2, Jun 2007, 3,984 KB)
altddio_DesignExample_ex1.zip ( 111 KB)
altddio_DesignExample_ex2.zip ( 139 KB)
altddio_ex1_msim.zip ( 17 KB)
altddio_ex2_msim.zip ( 17 KB)
- PowerPlay Early Power Estimator User Guide for Stratix, Stratix GX & Cyclone FPGAs (ver 2.0, Oct 2005, 649 KB)
- Stratix GX Transceiver User Guide (ver 3.0, Jan 2005, 8,044 KB)
- Seriallite MegaCore Function User Guide (ver 1.0.0, Sep 2004, 942 KB)
- High-Speed Development Kit, Stratix GX Edition User Guide (ver 1.0, Aug 2003, 6,325 KB)
Manuals
Application Notes
- AN 326: Interfacing QDRII+ & QDRII with Stratix II, Stratix II GX, Stratix, & Stratix GX Devices (ver 5.1, May 2008, 2,521 KB)
- AN 311: ASIC-to-FPGA Design Methodology and Guidelines (ver 2.0, Oct 2007, 415 KB)
- AN 471: High-Performance FPGA PLL Analysis with TimeQuest (ver 1.0, Jul 2007, 226 KB)
- AN 357: Error Detection & Recovery Using CRC in Altera FPGA Devices (ver 1.3, Feb 2007, 178 KB)
- AN 282: Implementing PLL Reconfiguration in Stratix & Stratix GX Devices (ver 2.0, Dec 2005, 511 KB)
Example 1: Shift Register in LEs ( 340 KB)
Example 2: altpll_reconfig Design with the MIF ( 192 KB)
Example 3: altpll_reconfig Design ( 191 KB)
- AN 342: Interfacing DDR SDRAM with Stratix & Stratix GX Devices (ver 2.0, Dec 2005, 428 KB)
- AN 325: Interfacing RLDRAM II with Stratix II, Stratix & Stratix GX Devices (ver 3.1, Nov 2005, 1,625 KB)
- AN 385: Using Stratix GX Transceivers for PCI Express (ver 1.0, Jun 2005, 3,695 KB)
- AN 382: Using Stratix GX Transceivers for CPRI (ver 1.0, May 2005, 953 KB)
- AN 360: Updating Simulation Models for the POS-PHY Level 4 MegaCore Function (ver 1.1, Dec 2004, 62 KB)
- AN 306: Implementing Multipliers in FPGA Devices (ver 3.0, Jul 2004, 732 KB)
- AN 349: QDR SRAM Controller Reference Design for Stratix & Stratix GX Devices (ver 1.0, May 2004, 280 KB)
- AN 227: SPI-4.2 Interoperability with the Intel IXF1110 in Stratix GX Devices (ver 1.0, May 2003, 455 KB)
- AN 228: SPI-4.2 Interoperability with PMC-Sierra XENON Family in Stratix GX Devices (ver 1.0, May 2003, 632 KB)
- AN 236: Using Source-Synchronous Signaling with DPA in Stratix GX Devices (ver 1.1, Jan 2003, 176 KB)
White Papers
- Basic Principles of Signal Integrity (ver 1.3, Dec 2007, 547 KB)
- Hot-Socketing & Power-Sequencing Feature & Testing for Altera Devices (ver 1.1, May 2006, 319 KB)
- Compromises of Using a 10-Gbps Transceiver at Other Data Rates (ver 1.0, Jul 2005, 100 KB)
- Input Signal Edge Rate Guidance (ver 1.0, Jun 2005, 62 KB)
- Using Parity to Detect Memory Errors in Stratix Devices (ver 1.2, Feb 2005, 96 KB)
- Transient Voltage Protection for Stratix GX Devices (ver 1.0, Jan 2005, 282 KB)
- The Benefits of Altera’s High-Speed DDR SDRAM Memory Interface Solution (ver 1.1, May 2004, 358 KB)
- Implementing a Queue Manager in Traffic Management Systems (ver 1.1, Feb 2004, 124 KB)
- Altera Hot-Socketing & Power-Sequencing Advantages (ver 1.2, Feb 2004, 79 KB)
- Selecting the Correct High Speed Transceiver Solution (ver 1.0, Sep 2003, 1,764 KB)
- Using Pre-Emphasis and Equalization with Stratix GX (ver 1.0, Sep 2003, 1,897 KB)
- Traffic Management in Stratix GX Devices (ver 1.0, Dec 2002, 69 KB)
- Stratix GX in Storage Applications (ver 1.0, Nov 2002, 80 KB)
- Stratix GX in Switch Fabric Systems (ver 1.0, Nov 2002, 222 KB)
- The Evolution of High Speed Transceiver Technology (ver 1.0, Nov 2002, 438 KB)
Selector Guides
Errata Sheets
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Literature
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