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Home > Products > Literature > SOPC Builder Print This Page Subscribe to Email Literature: SOPC Builder This page provides links to the SOPC Builder volume of the Quartus® II Development Software Handbook and other documents related to SOPC Builder. The SOPC Builder volume provides an introduction to all SOPC Builder features, complete usage reference, and tutorials for building custom systems. Click the links below to view and download the entire volume, or any individual section or chapter. For more SOPC Builder support, visit the SOPC Builder Support web page. Quartus II Handbook Volume 4: SOPC Builder (ver 7.2, Oct 2007, 1,894 KB) Section I. SOPC Builder Features (1,017 KB) Chapter 1. Introduction to SOPC Builder (ver 7.2.0, Oct 2007, 130 KB) Chapter 2. System Interconnect Fabric for Memory-Mapped Interfaces (ver 7.2.0, Oct 2007, 365 KB) Chapter 3. System Interconnect Fabric for Streaming Interfaces (ver 7.2.0, Oct 2007, 146 KB) Chapter 4. SOPC Builder Components (ver 7.2.0, Oct 2007, 107 KB) Chapter 5. Component Editor (ver 7.2.0, Oct 2007, 139 KB) Chapter 6. Building a Component Interface with Tcl Scripting Commands (ver 7.2.0, Oct 2007, 153 KB) Design Example Chapter 7. Archiving SOPC Builder Projects (ver 7.2.0, Oct 2007, 110 KB) Section II. Building Systems with SOPC Builder (1,113 KB) Chapter 8. Building Memory Subsystems Using SOPC Builder (ver 7.2.0, Oct 2007, 512 KB) Chapter 9. Developing Components for SOPC Builder (ver 7.2.1, Oct 2007, 347 KB) Design Example Section III. Interconnect Components (713 KB) Chapter 10. Avalon Memory-Mapped Bridges (ver 7.2.0, Oct 2007, 201 KB) Chapter 11. Avalon Streaming Interconnect Components (ver 7.2.0, Oct 2007, 210 KB) Quartus II Handbook Volume 5: Embedded Peripherals (ver 7.2, Oct 2007, 2,421 KB) Section I. Memory Peripherals (1,532 KB) Chapter 1. SDRAM Controller Core (ver 7.2.0, Oct 2007, 284 KB) Chapter 2. CompactFlash Core (ver 7.2.0, Oct 2007, 120 KB) Chapter 3. Common Flash Interface Controller Core (ver 7.2.0, Oct 2007, 107 KB) Chapter 4. EPCS Device Controller Core (ver 7.2.0, Oct 2007, 111 KB) Chapter 5. On-Chip FIFO Memory Core (ver 7.2.0, Oct 2007, 256 KB) Chapter 6. Scatter-Gather DMA Controller Core (ver 7.2.1, Jan 2008, 286 KB) Chapter 7. DMA Controller Core (ver 7.2.0, Oct 2007, 196 KB) Section II. Communication Peripherals (1,311 KB) Chapter 8. JTAG UART Core (ver 7.2.0, Oct 2007, 197 KB) Chapter 9. UART Core (ver 7.2.0, Oct 2007, 263 KB) Chapter 10. SPI Core (ver 7.2.0, Oct 2007, 242 KB) Section III. Display Peripherals (1,026 KB) Chapter 11. Optrex 16207 LCD Character Controller Core (ver 7.2.0, Oct 2007, 100 KB) Chapter 12. Video Sync Generator and Pixel Converter Cores (ver 7.2.0, Oct 2007, 117 KB) Section IV. Multiprocessor Coordination Peripherals (1,035 KB) Chapter 13. Mutex Core (ver 7.2.0, Oct 2007, 113 KB) Chapter 14. Mailbox Core (ver 7.2.0, Oct 2007, 125 KB) Section V. Other Memory-Mapped Peripherals (1,185 KB) Chapter 15. PIO Core (ver 7.2.0, Oct 2007, 142 KB) Chapter 16. Timer Core (ver 7.2.0, Oct 2007, 150 KB) Chapter 17. System ID Core (ver 7.2.0, Oct 2007, 88 KB) Chapter 18. PLL Core (ver 7.2.0, Oct 2007, 118 KB) Chapter 19. Performance Counter Core (ver 7.2.0, Oct 2007, 179 KB) Section VI. Streaming Peripherals (1,135 KB) Chapter 20. Avalon Streaming Channel Multiplexer and Demultiplexer Cores (ver 7.2.0, Oct 2007, 156 KB) Chapter 21. Avalon Streaming Test Pattern Generator and Checker Cores (ver 7.2.0, Oct 2007, 268 KB) Embedded Design Handbook (ver 1.0, Mar 2008, 4,663 KB) Section I. Introduction (382 KB) Chapter 1. First-Time Designer's Guide (ver 1.0, Mar 2008, 366 KB) Section II. Nios II Software Development (3,239 KB) Chapter 2. Developing Nios II Software (ver 1.0, Mar 2008, 787 KB) Chapter 3. Debugging Nios II Designs (ver 1.0, Mar 2008, 1,561 KB) Chapter 4. Nios II Command-Line Tools (ver 1.0, Mar 2008, 373 KB) Chapter 5. Optimizing Nios II C2H Compiler Results (ver 1.0, Mar 2008, 687 KB) edh_c2h_optimization_design_files.zip Section III. System Level Design (993 KB) Chapter 6. Avalon Memory-Mapped Design Optimizations (ver 1.0, Mar 2008, 416 KB) Chapter 7. Memory System Design (ver 1.0, Mar 2008, 248 KB) Chapter 8. Hardware Acceleration and Coprocessing (ver 1.0, Mar 2008, 234 KB) Chapter 9. Verification and Board Bring-Up (ver 1.0, Mar 2008, 269 KB) Related Documentation User Guides Nios II Custom Instruction User Guide (ver 1.4, May 2007, 715 KB) Application Notes AN 323: Using SignalTap II Embedded Logic Analyzers in SOPC Builder Systems (ver 1.1, Nov 2007, 385 KB) AN 398: Using DDR/DDR2 SDRAM With SOPC Builder (ver 1.1, Aug 2006, 775 KB) AN 397: Interfacing to External Processors (ver 1.0, Aug 2005, 362 KB)      AN 397: Interfacing to External Processors Design Files ( 12 KB) White Papers Comparing IP Integration Approaches for FPGA Implementation (ver 1.1, Feb 2008, 194 KB) Selector Guides Altera Product Catalog 2007 (ver 4.1, Sep 2007, 2,597 KB) Functional Specifications Avalon Interface Specifications (ver 1.0, Mar 2008, 583 KB) (Replaces "Avalon Memory-Mapped Interface Specification" and "Avalon Streaming Interface Specification") Tutorials Nios II Hardware Development Tutorial (ver 2.5, Oct 2007, 922 KB)      Design Files for Cyclone EP1C12 ( 5 KB)      Design Files for Cyclone EP1C20 ( 6 KB)      Design Files for Cyclone II EP2C35 ( 6 KB)      Design Files for Stratix EP1S10 ( 6 KB)      Design Files for Stratix EP1S10ES ( 6 KB)      Design Files for Stratix EP1S40 ( 6 KB)      Design Files for Stratix II EP2S60 ( 5 KB)      Design Files for Stratix II EP2S60ES ( 6 KB)      Design Files for Stratix II EP2S60 ROHS ( 5 KB) Product Overview 1080p video framework from Altera (ver 1.0, Apr 2008, 229 KB) Broadcast Solutions Supporting Altera's HD Quality Initiative (HDQI) (ver 2.0, Apr 2008, 1,703 KB) Accelerating applications on coprocessing platforms (ver 1.0, Jul 2007, 103 KB) Industrial Ethernet solutions from Altera (ver 1.0, Mar 2007, 114 KB) Rate This Page

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