Literature: SOPC Builder
This page provides links to the SOPC Builder volume of the Quartus® II Development Software Handbook and other documents related to SOPC Builder. The SOPC Builder volume provides an introduction to all SOPC Builder features, complete usage reference, and tutorials for building custom systems. Click the links below to view and download the entire volume, or any individual section or chapter. For more SOPC Builder support, visit the SOPC Builder Support web page.
Section I.
SOPC Builder Features (1,017 KB)
- Chapter 1. Introduction to SOPC Builder (ver 7.2.0, Oct 2007, 130 KB)
- Chapter 2. System Interconnect Fabric for Memory-Mapped Interfaces (ver 7.2.0, Oct 2007, 365 KB)
- Chapter 3. System Interconnect Fabric for Streaming Interfaces (ver 7.2.0, Oct 2007, 146 KB)
- Chapter 4. SOPC Builder Components (ver 7.2.0, Oct 2007, 107 KB)
- Chapter 5. Component Editor (ver 7.2.0, Oct 2007, 139 KB)
- Chapter 6. Building a Component Interface with Tcl Scripting Commands (ver 7.2.0, Oct 2007, 153 KB)
- Chapter 7. Archiving SOPC Builder Projects (ver 7.2.0, Oct 2007, 110 KB)
Section II.
Building Systems with SOPC Builder (1,113 KB)
Section III.
Interconnect Components (713 KB)
Section I.
Memory Peripherals (1,532 KB)
- Chapter 1. SDRAM Controller Core (ver 7.2.0, Oct 2007, 284 KB)
- Chapter 2. CompactFlash Core (ver 7.2.0, Oct 2007, 120 KB)
- Chapter 3. Common Flash Interface Controller Core (ver 7.2.0, Oct 2007, 107 KB)
- Chapter 4. EPCS Device Controller Core (ver 7.2.0, Oct 2007, 111 KB)
- Chapter 5. On-Chip FIFO Memory Core (ver 7.2.0, Oct 2007, 256 KB)
- Chapter 6. Scatter-Gather DMA Controller Core (ver 7.2.1, Jan 2008, 286 KB)
- Chapter 7. DMA Controller Core (ver 7.2.0, Oct 2007, 196 KB)
Section II.
Communication Peripherals (1,311 KB)
- Chapter 8. JTAG UART Core (ver 7.2.0, Oct 2007, 197 KB)
- Chapter 9. UART Core (ver 7.2.0, Oct 2007, 263 KB)
- Chapter 10. SPI Core (ver 7.2.0, Oct 2007, 242 KB)
Section III.
Display Peripherals (1,026 KB)
Section IV.
Multiprocessor Coordination Peripherals (1,035 KB)
Section V.
Other Memory-Mapped Peripherals (1,185 KB)
- Chapter 15. PIO Core (ver 7.2.0, Oct 2007, 142 KB)
- Chapter 16. Timer Core (ver 7.2.0, Oct 2007, 150 KB)
- Chapter 17. System ID Core (ver 7.2.0, Oct 2007, 88 KB)
- Chapter 18. PLL Core (ver 7.2.0, Oct 2007, 118 KB)
- Chapter 19. Performance Counter Core (ver 7.2.0, Oct 2007, 179 KB)
Section VI.
Streaming Peripherals (1,135 KB)
Section I.
Introduction (382 KB)
Section II.
Nios II Software Development (3,239 KB)
Section III.
System Level Design (993 KB)
Related Documentation
User Guides
Application Notes
White Papers
Selector Guides
Functional Specifications
- Avalon Interface Specifications (ver 1.0, Mar 2008, 583 KB)
(Replaces "Avalon Memory-Mapped Interface Specification" and "Avalon Streaming Interface Specification")
Tutorials
Product Overview
|