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Home > Products > Literature > Stratix IV (E and GX) Print This Page Subscribe to Email Literature: Stratix IV Devices Package Specifications Thermal Specifications Known Stratix® IV Issues Family Overview (PDF) Datasheet (PDF) Upcoming Device Features (PDF) Stratix IV Device Handbook (11 MB) Show All / Hide All Volume 1 - Stratix IV Device Handbook (ver 1.0, May 2008, 4 MB) Section I. Device Core (1 MB) Chapter 1. Stratix IV Device Family Overview (ver 1.0, May 2008, 195 KB) Chapter 2. Logic Array Blocks and Adaptive Logic Modules in Stratix IV Devices (ver 1.0, May 2008, 208 KB) Chapter 3. TriMatrix Embedded Memory Blocks in Stratix IV Devices (ver 1.0, May 2008, 273 KB) Chapter 4. DSP Blocks in Stratix IV Devices (ver 1.0, May 2008, 345 KB) Chapter 5. Clock Networks and PLLs in Stratix IV Devices (ver 1.0, May 2008, 625 KB) Section II. I/O Interfaces (1 MB) Chapter 6. I/O Features in Stratix IV Devices (ver 1.0, May 2008, 634 KB) Chapter 7. External Memory Interfaces in Stratix IV Devices (ver 1.0, May 2008, 506 KB) Chapter 8. High Speed Differential I/O Interfaces with DPA in Stratix IV Devices (ver 1.0, May 2008, 515 KB) Section III. System Integration (993 KB) Chapter 9. Hot Socketing and Power-On Reset in Stratix IV Devices (ver 1.0, May 2008, 93 KB) Chapter 10. Configuration, Design Security, Remote System Upgrades with Stratix IV Devices (ver 1.0, May 2008, 773 KB) Chapter 11. SEU Mitigation in Stratix IV Devices (ver 1.0, May 2008, 210 KB) Chapter 12. JTAG Boundary Scan Testing (ver 1.0, May 2008, 110 KB) Chapter 13. Power Management in Stratix IV Devices (ver 1.0, May 2008, 137 KB) Volume 2 - Stratix IV Device Handbook (ver 1.0, May 2008, 4 MB) Section I. Transceiver Architecture (3 MB) Chapter 1. Stratix IV Transceiver Architecture (ver 1.0, May 2008, 2 MB) Chapter 2. Stratix IV Transceiver Clocking (ver 1.0, May 2008, 2 MB) Chapter 3. Configuring Multiple Protocols and Data Rates (ver 1.0, May 2008, 216 KB) Chapter 4. Reset Control and Power Down (ver 1.0, May 2008, 191 KB) Volume 3 - Stratix IV Device Handbook (ver 1.1, May 2008, 3 MB) Section I. Transceiver Configuration Guide (3 MB) Chapter 1. ALTGX Transceiver Setup Guide (ver 1.1, May 2008, 3 MB) Chapter 2. Transceiver Design Flow Guide (ver 1.0, May 2008, 647 KB) Volume 4 - Stratix IV Device Datasheet (ver 1.0, May 2008, 953 KB) Section I. Device Datasheet (827 KB) Chapter 1. DC and Switching Characteristics (ver 1.0, May 2008, 865 KB) Related Documentation Power and Thermal Management Altera at 40 nm: Jitter-, Signal Integrity-, Power-, and Process-Optimized Transceivers (ver 1.0, May 2008, 3 MB) AN 514: Power Optimization in Stratix IV FPGAs (ver 1.0, May 2008, 221 KB) Power Delivery Network (PDN) Tool User Guide (ver 1.0, May 2008, 963 KB)      Power Delivery Network (PDN) Tool (1 MB) PowerPlay Early Power Estimator User Guide For Stratix III and Stratix IV FPGAs (ver 2.0, May 2008, 1 MB) Stratix IV FPGA Power Management and Advantages (ver 1.0, May 2008, 2 MB) I/O Interfaces, Protocols and Signal Integrity AN 528: PCB Dielectric Material Selection and Fiber Weave Effect on High-Speed Channel Routing (ver 1.0, May 2008, 1 MB) AN 529: Via Optimization Techniques for High-Speed Channel Designs (ver 1.0, May 2008, 690 KB) AN 530: Optimizing Impedence Discontinuity Caused by Surface Mount Pads for High-Speed Channel Designs (ver 1.0, May 2008, 208 KB) PCI Express Compiler User Guide (ver 8.0, May 2008, 2 MB) Altera at 40 nm: Jitter-, Signal Integrity-, Power-, and Process-Optimized Transceivers (ver 1.0, May 2008, 3 MB) Triple Speed Ethernet MegaCore Function User Guide (ver 8.0, May 2008, 1 MB) DSP think AND not OR - Altera at 40 nm brochure (ver 1.0, May 2008, 380 KB) General Device Documentation think AND not OR - Altera at 40 nm brochure (ver 1.0, May 2008, 380 KB) Altera at 40 nm: Jitter-, Signal Integrity-, Power-, and Process-Optimized Transceivers (ver 1.0, May 2008, 3 MB) Leveraging the 40-nm Process Node to Deliver the World's Most Advanced Custom Logic Devices (ver 1.0, May 2008, 371 KB) Training Courses Serial RapidIO Design with Stratix IV GX FPGAs Ethernet Design with Stratix IV GX FPGAs PCI Express Design with Stratix IV GX FPGAs Rate This Page

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