Literature: Stratix Device Handbook
The Stratix® Device Handbook is comprised of two volumes. Volume 1 is the Stratix FPGA family data sheet; Volume 2 contains detailed information on how to use Stratix features. To view all two volumes, click the link below.
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Check the Knowledge Database for Known Issues with the Stratix Handbook.
Volume 1 (ver 3.4, Jan 2006, 3,554 KB)
Section I.
Stratix Device Family Data Sheet (3,318 KB)
- Chapter 1. Introduction (ver 3.2, Jul 2005, 110 KB)
- Chapter 2. Stratix Architecture (ver 3.3, Jul 2005, 1,287 KB)
- Chapter 3. Configuration & Testing (ver 1.3, Jul 2005, 181 KB)
- Chapter 4. DC & Switching Characteristics (ver 3.4, Jan 2006, 1,863 KB)
- Chapter 5. Reference & Ordering Information (ver 2.1, Sep 2004, 58 KB)
Volume 2 (ver 3.5, Jun 2006, 6,307 KB)
Section I.
Clock Management (692 KB)
Section II.
Memory (525 KB)
Section III.
I/O Standards (1,273 KB)
Section IV.
Digital Signal Processing (DSP) (951 KB)
Section V.
IP & Design Considerations (658 KB)
Section VI.
Configuration & Remote System Upgrades (1,036 KB)
Section VII.
PCB Layout Guidelines (625 KB)
Related Documentation
Data Sheets
- Stratix GX FPGA Family Data Sheet (ver 2.2, Dec 2004, 1,639 KB)
- Altera Device Package Information Data Sheet (ver 15.0, Apr 2008, 4,246 KB)
- Stratix Series Device Thermal Resistance (ver 4.0, Jan 2008, 164 KB)
- Stratix EP1S25 DSP Development Board Data Sheet (ver 1.6, Dec 2004, 663 KB)
- Stratix PCI Development Board Data Sheet (ver 2.0, Sep 2003, 2,064 KB)
User Guides
- Double Data Rate I/O Megafunction User Guide (ALTDDIO_IN, ALTDDIO_OUT, and ALTDDIO_BIDIR) (ver 4.2, Jun 2007, 3,984 KB)
altddio_DesignExample_ex1.zip ( 111 KB)
altddio_DesignExample_ex2.zip ( 139 KB)
altddio_ex1_msim.zip ( 17 KB)
altddio_ex2_msim.zip ( 17 KB)
- First-In-First-Out Megafunction User Guide (FIFO) (ver 4.0, May 2007, 959 KB)
dcfifo_in_legacy_mode.qar ( 268 KB)
dcfifo_in_show_ahead_mode.qar ( 223 KB)
dcfifo_narrow_write_wide_read.qar ( 227 KB)
dcfifo_wide_write_narrow_read.qar ( 231 KB)
scfifo_in_legacy_mode.qar ( 36 KB)
scfifo_in_show_ahead_mode.qar ( 37 KB)
- PowerPlay Early Power Estimator User Guide for Stratix, Stratix GX & Cyclone FPGAs (ver 2.0, Oct 2005, 649 KB)
- First-In-First-Out Partitioner Megafunction User Guide (FIFO Partitioner) (ver 1.2, Aug 2005, 306 KB)
- PCI High-Speed Development Kit, Stratix Professional Edition Getting Started User Guide (ver 1.0.0, Sep 2003, 1,998 KB)
Application Notes
- AN 326: Interfacing QDRII+ & QDRII with Stratix II, Stratix II GX, Stratix, & Stratix GX Devices (ver 5.0, Mar 2008, 2,521 KB)
- AN 114: Designing with High-Density BGA Packages for Altera Devices (ver 5.1, Dec 2007, 574 KB)
- AN 311: ASIC-to-FPGA Design Methodology and Guidelines (ver 2.0, Oct 2007, 415 KB)
- AN 471: High-Performance FPGA PLL Analysis with TimeQuest (ver 1.0, Jul 2007, 226 KB)
- AN 357: Error Detection & Recovery Using CRC in Altera FPGA Devices (ver 1.3, Feb 2007, 178 KB)
- AN 344: ASI Demonstration (ver 2.0, Oct 2006, 145 KB)
- AN 282: Implementing PLL Reconfiguration in Stratix & Stratix GX Devices (ver 2.0, Dec 2005, 511 KB)
Example 1: Shift Register in LEs ( 340 KB)
Example 2: altpll_reconfig Design with the MIF ( 192 KB)
Example 3: altpll_reconfig Design ( 191 KB)
- AN 342: Interfacing DDR SDRAM with Stratix & Stratix GX Devices (ver 2.0, Dec 2005, 428 KB)
- AN 325: Interfacing RLDRAM II with Stratix II, Stratix & Stratix GX Devices (ver 3.1, Nov 2005, 1,625 KB)
- AN 360: Updating Simulation Models for the POS-PHY Level 4 MegaCore Function (ver 1.1, Dec 2004, 62 KB)
- AN 356: Serial Digital Interface Reference Design for Cyclone & Stratix Devices (ver 1.1, Aug 2004, 155 KB)
- AN 306: Implementing Multipliers in FPGA Devices (ver 3.0, Jul 2004, 732 KB)
- AN 349: QDR SRAM Controller Reference Design for Stratix & Stratix GX Devices (ver 1.0, May 2004, 280 KB)
- AN 329: ZBT SRAM Controller Reference Design for Stratix & Stratix GX Devices (ver 1.0, Mar 2004, 165 KB)
- AN 315: Guidelines for Designing High-Speed FPGA PCBs (ver 1.1, Feb 2004, 1,814 KB)
- AN 313: Implementing Clock Switchover in Stratix & Stratix GX Devices (ver 1.0, Jan 2004, 273 KB)
Clock Switchover Example Design ( 233 KB)
- AN 247: Stratix GX to Mercury Interoperability (ver 1.2, Jan 2004, 81 KB)
- AN 336: Using External Series and Parallel Termination with Stratix and Stratix GX Devices (ver 1.0, Nov 2003, 1,425 KB)
- AN 210: Converting Memory from Asynchronous to Synchronous for Stratix & Stratix GX Designs (ver 2.0, Nov 2002, 143 KB)
- AN 207: TriMatrix Memory Selection Using the Quartus II Software (ver 2.1, Nov 2002, 323 KB)
- AN 224: High-Speed Board Layout Guidelines (ver 1.0, Nov 2002, 895 KB)
White Papers
- Hot-Socketing & Power-Sequencing Feature & Testing for Altera Devices (ver 1.1, May 2006, 319 KB)
- Input Signal Edge Rate Guidance (ver 1.0, Jun 2005, 62 KB)
- Using Parity to Detect Memory Errors in Stratix Devices (ver 1.2, Feb 2005, 96 KB)
- Stratix vs. Virtex-II Pro FPGA Performance Analysis (ver 1.1, Nov 2004, 146 KB)
- Using Stratix GX Devices for SONET/SDH Backplanes (ver 1.1, May 2004, 192 KB)
- Improving Pin-to-Pin Timing in Stratix & Stratix GX (ver 1.0, Apr 2004, 169 KB)
- The Need for Dynamic Phase Alignment in High-Speed FPGAs (ver 1.1, Feb 2004, 70 KB)
- Altera Hot-Socketing & Power-Sequencing Advantages (ver 1.2, Feb 2004, 79 KB)
- MorphIO: An I/O Reconfiguration Solution for Altera Devices (ver 1.0, May 2003, 46 KB)
Tcl File ( 5 KB)
Readme File ( 6 KB)
- An Analytical Review of FPGA Logic Efficiency in Stratix, Virtex-II & Virtex-II Pro Devices (ver 1.1, May 2003, 116 KB)
Brochures
Selector Guides
Errata Sheets
Technical Briefs
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Literature
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