Literature: Stratix Device Handbook

The Stratix^® Device Handbook is comprised of two volumes. Volume 1 is the Stratix FPGA family data sheet; Volume 2 contains detailed information on how to use Stratix features. To view all two volumes, click the link below.

Stratix Device Handbook (Complete Two-Volume Set) (10 MB)

Get more information on Stratix Pin-Outs.

Check the Knowledge Database for Known Issues with the Stratix Handbook.

Volume 1 (ver 3.4, Jan 2006, 3 MB)

Section I. Stratix Device Family Data Sheet (3 MB)

• Chapter 1. Introduction (ver 3.2, Jul 2005, 111 KB)
• Chapter 2. Stratix Architecture (ver 3.3, Jul 2005, 1 MB)
• Chapter 3. Configuration & Testing (ver 1.3, Jul 2005, 181 KB)
• Chapter 4. DC & Switching Characteristics (ver 3.4, Jan 2006, 2 MB)
• Chapter 5. Reference & Ordering Information (ver 2.1, Sep 2004, 59 KB)
• Stratix Device Pin-Out Files

Volume 2 (ver 3.5, Jun 2006, 6 MB)

Section I. Clock Management (693 KB)

• Chapter 1. General-Purpose PLLs in Stratix & Stratix GX Devices (ver 3.2, Jul 2005, 670 KB)
  (Replaces AN 200)

Section II. Memory (525 KB)

• Chapter 2. TriMatrix Embedded Memory Blocks in Stratix & Stratix GX Devices (ver 3.3, Jul 2005, 312 KB)
  (Replaces AN 203)
• Chapter 3. External Memory Interfaces in Stratix & Stratix GX Devices (ver 3.3, Jun 2006, 275 KB)
  (Replaces AN 212)

Section III. I/O Standards (1 MB)

• Chapter 4. Selectable I/O Standards in Stratix & Stratix GX Devices (ver 3.4, Jun 2006, 448 KB)
  (Replaces AN 201)
• Chapter 5. High-Speed Differential I/O Interfaces in Stratix Devices (ver 3.2, Jul 2005, 1,011 KB)
  (Replaces AN 202)

Section IV. Digital Signal Processing (DSP) (952 KB)

• Chapter 6. DSP Blocks in Stratix & Stratix GX Devices (ver 2.2, Jul 2005, 267 KB)
  (Replaces AN 214)
• Chapter 7. Implementing High-Performance DSP Functions in Stratix & Stratix GX Devices (ver 1.1, Sep 2004, 760 KB)
  (Replaces AN 215)

Section V. IP & Design Considerations (659 KB)

• Chapter 8. Implementing 10-Gigabit Ethernet Using Stratix & Stratix GX Devices (ver 2.0, Jul 2005, 265 KB)
  (Replaces AN 220)
• Chapter 9. Implementing SFI-4 in Stratix & Stratix GX Devices (ver 2.0, Jul 2005, 190 KB)
  (Replaces AN 219)
• Chapter 10. Transitioning APEX Designs to Stratix & Stratix GX Devices (ver 3.0, Jul 2005, 339 KB)
  (Replaces AN 206)

Section VI. Configuration & Remote System Upgrades (1 MB)

• Chapter 11. Configuring Stratix & Stratix GX Devices (ver 3.2, Jul 2005, 559 KB)
  (Replaces AN 208)
• Chapter 12. Remote System Configuration with Stratix & Stratix GX Devices (ver 3.1, Sep 2004, 682 KB)
  (Replaces AN 217)
• Reference Design

Section VII. PCB Layout Guidelines (625 KB)

• Chapter 13. Package Information for Stratix Devices (ver 3.0, Jul 2005, 398 KB)
• Chapter 14. Designing with 1.5-V Devices (ver 1.1, Jan 2005, 251 KB)

Related Documentation

Data Sheets

• Stratix GX FPGA Family Data Sheet (ver 2.2, Dec 2004, 2 MB)
• Altera Device Package Information Data Sheet (ver 15.7, Jun 2009, 6 MB)
• Stratix EP1S25 DSP Development Board Data Sheet (ver 1.6, Dec 2004, 663 KB)
• Stratix PCI Development Board Data Sheet (ver 2.0, Sep 2003, 2 MB)

User Guides

• Single- and Dual-Clock FIFO Megafunction User Guide (ver 5.1, Feb 2009, 486 KB)
• Double Data Rate I/O Megafunction User Guide (ALTDDIO_IN, ALTDDIO_OUT, and ALTDDIO_BIDIR) (ver 4.2, Jun 2007, 4 MB)
altddio_DesignExample_ex1.zip ( 112 KB)
altddio_DesignExample_ex2.zip ( 140 KB)
altddio_ex1_msim.zip ( 18 KB)
altddio_ex2_msim.zip ( 17 KB)
• PowerPlay Early Power Estimator User Guide for Stratix, Stratix GX & Cyclone FPGAs (ver 2.0, Oct 2005, 649 KB)
• First-In-First-Out Partitioner Megafunction User Guide (FIFO Partitioner) (ver 1.2, Aug 2005, 306 KB)
• PCI High-Speed Development Kit, Stratix Professional Edition Getting Started User Guide (ver 1.0.0, Sep 2003, 2 MB)

Manuals

• Advanced Synthesis Cookbook: A Design Guide for Stratix II, Stratix III, and Stratix IV Devices (ver 4.0, May 2008, 968 KB)
Advanced Synthesis Cookbook Design Files ( 3 MB)

Application Notes

• AN 326: Interfacing QDRII+ & QDRII with Stratix II, Stratix II GX, Stratix, & Stratix GX Devices (ver 5.1, May 2008, 2 MB)
• AN 311: ASIC-to-FPGA Design Methodology and Guidelines (ver 3.1, Apr 2009, 286 KB)
• AN 357: Error Detection & Recovery Using CRC in Altera FPGA Devices (ver 1.4, Jul 2008, 371 KB)
• AN 114: Designing with High-Density BGA Packages for Altera Devices (ver 5.1, Dec 2007, 574 KB)
• AN 344: ASI Demonstration (ver 2.0, Oct 2006, 145 KB)
• AN 282: Implementing PLL Reconfiguration in Stratix & Stratix GX Devices (ver 2.0, Dec 2005, 511 KB)
Example 1: Shift Register in LEs ( 340 KB)
Example 2: altpll_reconfig Design with the MIF ( 192 KB)
Example 3: altpll_reconfig Design ( 192 KB)
• AN 342: Interfacing DDR SDRAM with Stratix & Stratix GX Devices (ver 2.0, Dec 2005, 428 KB)
• AN 325: Interfacing RLDRAM II with Stratix II, Stratix & Stratix GX Devices (ver 3.1, Nov 2005, 2 MB)
• AN 360: Updating Simulation Models for the POS-PHY Level 4 MegaCore Function (ver 1.1, Dec 2004, 63 KB)
• AN 306: Implementing Multipliers in FPGA Devices (ver 3.0, Jul 2004, 733 KB)
• AN 349: QDR SRAM Controller Reference Design for Stratix & Stratix GX Devices (ver 1.0, May 2004, 280 KB)
• AN 329: ZBT SRAM Controller Reference Design for Stratix & Stratix GX Devices (ver 1.0, Mar 2004, 165 KB)
• AN 315: Guidelines for Designing High-Speed FPGA PCBs (ver 1.1, Feb 2004, 2 MB)
• AN 313: Implementing Clock Switchover in Stratix & Stratix GX Devices (ver 1.0, Jan 2004, 273 KB)
Clock Switchover Example Design ( 233 KB)
• AN 247: Stratix GX to Mercury Interoperability (ver 1.2, Jan 2004, 82 KB)
• AN 336: Using External Series and Parallel Termination with Stratix and Stratix GX Devices (ver 1.0, Nov 2003, 1 MB)
• AN 210: Converting Memory from Asynchronous to Synchronous for Stratix & Stratix GX Designs (ver 2.0, Nov 2002, 143 KB)
• AN 224: High-Speed Board Layout Guidelines (ver 1.0, Nov 2002, 896 KB)

White Papers

• Crest Factor Reduction for OFDM-Based Wireless Systems (ver 1.0, Dec 2008, 164 KB)
• FPGA Performance Benchmarking Methodology (ver 1.6, Aug 2007, 246 KB)
• Hot-Socketing & Power-Sequencing Feature & Testing for Altera Devices (ver 1.1, May 2006, 319 KB)
• Input Signal Edge Rate Guidance (ver 1.0, Jun 2005, 63 KB)
• Using Parity to Detect Memory Errors in Stratix Devices (ver 1.2, Feb 2005, 97 KB)
• Stratix vs. Virtex-II Pro FPGA Performance Analysis (ver 1.1, Nov 2004, 146 KB)
• Using Stratix GX Devices for SONET/SDH Backplanes (ver 1.1, May 2004, 193 KB)
• Improving Pin-to-Pin Timing in Stratix & Stratix GX (ver 1.0, Apr 2004, 170 KB)
• The Need for Dynamic Phase Alignment in High-Speed FPGAs (ver 1.1, Feb 2004, 71 KB)
• Altera Hot-Socketing & Power-Sequencing Advantages (ver 1.2, Feb 2004, 79 KB)
• MorphIO: An I/O Reconfiguration Solution for Altera Devices (ver 1.0, May 2003, 46 KB)
Tcl File ( 5 KB)
Readme File ( 7 KB)
• An Analytical Review of FPGA Logic Efficiency in Stratix, Virtex-II & Virtex-II Pro Devices (ver 1.1, May 2003, 117 KB)

Selector Guides

• Stratix FPGA Series Package & I/O Matrix (ver 1.0, Aug 2006, 75 KB)

Errata Sheets

• Stratix FPGA Errata Sheet (ver 3.1, Jan 2007, 229 KB)
Example 1: Clock Switchover ( 979 KB)
Example 2: Gated Lock ( 973 KB)

Technical Briefs

• TB 089: Extended Temperature Support for MAX 7000AE, Cyclone, Stratix, and ACEX 1K Devices (ver 1.0, Jan 2007, 201 KB)

Product Overview

• Altera Enhanced COTS PLD Initiative (ver 1.1, Jul 2008, 122 KB)

Process Change Notifications

• PCN 0902 Additional Assembly Source and Bill of Material Change for Altera Flip Chip Products (Apr 2009, 591 KB)