Literature: Stratix II Devices

The Stratix^® II Device Handbook is comprised of two volumes. Volume 1 is the Stratix II FPGA family data sheet. Volume 2 provides detailed information on Stratix II features, and PCB layout guidelines. To view both volumes, click the link below.

Get more information on Stratix II Pin-Outs.

Check the Knowledge Database for Known Issues with the Stratix II Handbook.

Stratix II Device Handbook (Complete Two-Volume Set) (4 MB)

Stratix II Device Handbook, Volume 1 (ver 4.4, Jul 2009, 1 MB)

Section I. Stratix II Device Family Data Sheet (1 MB)

• Chapter 1. Introduction (ver 4.2, Jul 2007, 132 KB)
• Chapter 2. Stratix II Architecture (ver 4.3, May 2007, 1,011 KB)
• Chapter 3. Configuration & Testing (ver 4.2, May 2007, 165 KB)
• Chapter 4. Hot Socketing & Power-On Reset (ver 3.2, Apr 2006, 102 KB)
• Chapter 5. DC & Switching Characteristics (ver 4.4, Jul 2009, 592 KB)
• Chapter 6. Reference & Ordering Information (ver 2.1, May 2007, 70 KB)

Stratix II Device Handbook, Volume 2 (ver 4.5, Jul 2009, 3 MB)

Section I. Clock Management (818 KB)

• Chapter 1. PLLs in Stratix II and Stratix II GX Devices (ver 4.6, Jul 2009, 634 KB)

Section II. Memory (701 KB)

• Chapter 2. TriMatrix Embedded Memory Blocks in Stratix II and Stratix II GX Devices (ver 4.5, Jan 2008, 376 KB)
• Chapter 3. External Memory Interfaces in Stratix II and Stratix II GX Devices (ver 4.5, Jan 2008, 387 KB)

Section III. I/O Standards (748 KB)

• Chapter 4. Selectable I/O Standards in Stratix II and Stratix II GX Devices (ver 4.6, Jan 2008, 491 KB)
• Chapter 5. High-Speed Differential I/O Interfaces with DPA in Stratix II and Stratix II GX Devices (ver 2.2, Jan 2008, 337 KB)

Section IV. Digital Signal Processing (DSP) (348 KB)

• Chapter 6. DSP Blocks in Stratix II and Stratix II GX Devices (ver 2.2, Jan 2008, 339 KB)

Section V. Configuration and Remote System Upgrades (1 MB)

• Chapter 7. Configuring Stratix II and Stratix II GX Devices (ver 4.5, Jan 2008, 993 KB)
• Chapter 8. Remote System Upgrades with Stratix II and Stratix II GX Devices (ver 4.5, Jan 2008, 291 KB)
• Chapter 9. IEEE 1149.1 (JTAG) Boundary Scan Testing in Stratix II and Stratix II GX Devices (ver 3.3, Jan 2008, 272 KB)

Section VI. PCB Layout Guidelines (1 MB)

• Chapter 10. Package Information for Stratix II & Stratix II GX Devices (ver 4.3, May 2007, 477 KB)
• Chapter 11. High-Speed Board Layout Guidelines (ver 1.4, May 2007, 654 KB)

Related Documentation

Data Sheets

• Altera Device Package Information Data Sheet (ver 16.0, Dec 2009, 12 MB)

User Guides

• SCFIFO and DCFIFO Megafunctions User Guide (ver 6.1, Jan 2010, 395 KB)
DCFIFO Design Example ( 33 KB)
• External Memory PHY Interface (ALTMEMPHY) (nonAFI) Megafunction User Guide (ver 7.3, Jan 2010, 3 MB)
• DDR Timing Wizard User Guide (ver 3.0, Nov 2007, 2 MB)
• Double Data Rate I/O Megafunction User Guide (ALTDDIO_IN, ALTDDIO_OUT, and ALTDDIO_BIDIR) (ver 4.2, Jun 2007, 4 MB)
altddio_DesignExample_ex1.zip ( 112 KB)
altddio_DesignExample_ex2.zip ( 140 KB)
altddio_ex1_msim.zip ( 18 KB)
altddio_ex2_msim.zip ( 17 KB)
• PowerPlay Early Power Estimator User Guide for Stratix II, Stratix II GX, and HardCopy II (ver 1.2, Jan 2007, 3 MB)

Manuals

• Advanced Synthesis Cookbook: A Design Guide for Stratix II, Stratix III, and Stratix IV Devices (ver 5.0, Jul 2008, 2 MB)
Advanced Synthesis Cookbook Design Files ( 4 MB)
• Nios Development Board Stratix II Edition Reference Manual (ver 1.3, May 2007, 1 MB)
  (RoHS Compliant)
Nios Development Board Stratix II Edition PCB Layout Files ( 5 MB)
Nios Development Board Stratix II Edition Schematic ( 789 KB)
• Stratix II EP2S180 DSP Development Board Reference Manual (ver 1.0, Aug 2005, 549 KB)

Application Notes

• AN 328: Interfacing DDR2 SDRAM with Stratix II, Stratix II GX, and Arria GX Devices (ver 6.0, Oct 2009, 3 MB)
ALTMEMPHY Example ( 604 KB)
Legacy PHY Example ( 330 KB)
• AN 326: Interfacing QDRII+ & QDRII with Stratix II, Stratix II GX, Stratix, & Stratix GX Devices (ver 5.1, May 2008, 2 MB)
• AN 517: Using High-Performance DDR, DDR2, DDR3 SDRAM with SOPC Builder (ver 1.0, Apr 2008, 1 MB)
AN 517 Design Files ( 2 MB)
• AN 432: Using Different PLL Settings Between Stratix II and HardCopy II Devices (ver 1.1, Dec 2007, 168 KB)
• AN 477: Designing RGMII Interface with FPGA and HardCopy Devices (ver 2.0, Jan 2010, 519 KB)
• AN 358: Thermal Management for FPGAs (ver 2.0, Dec 2009, 260 KB)
• AN 341: Using the Design Security Feature in Stratix II and Stratix II GX Devices (ver 2.3, Sep 2009, 1 MB)
• AN 444: Dual DIMM DDR2 SDRAM Interface Design Guidelines (ver 1.1, May 2009, 7 MB)
• AN 367: Implementing PLL Reconfiguration in Stratix II Devices (ver 2.1, May 2009, 717 KB)
Example 1: altpll_reconfig Design with the MIF ( 244 KB)
Example 2: altpll_reconfig Design with Write Parameters ( 249 KB)
Example 3: altpll_reconfig Design for Phase Shift Stepping ( 251 KB)
• AN 462: Implementing Multiple Memory Interfaces Using the ALTMEMPHY Megafunction (ver 1.3, Apr 2009, 784 KB)
Example Design for AN 462: top.qar ( 715 KB)
• AN 550: Using the DLL Phase Offset Feature in Stratix II and HardCopy II Devices (ver 1.0, Nov 2008, 598 KB)
altmemphy_ext_dll.zip ( 48 KB)
altmemphy_int_dll.zip ( 47 KB)
static_dll.zip ( 18 KB)
• AN 327: Interfacing DDR SDRAM with Stratix II Devices (ver 3.2, Sep 2008, 938 KB)
• AN 357: Error Detection & Recovery Using CRC in Altera FPGA Devices (ver 1.4, Jul 2008, 371 KB)
• AN 408: DDR2 Memory Interface Termination, Drive Strength, Loading, and Design Layout Guidelines (ver 2.1, Jul 2008, 4 MB)
SII Simulation Example ( 3 KB)
SIII Simulation Example ( 3 KB)
• AN 114: Designing with High-Density BGA Packages for Altera Devices (ver 5.1, Dec 2007, 574 KB)
• AN 449: External Memory Interface Design Guidelines for Stratix II, Stratix II GX, and Arria GX Devices (ver 1.2, Sep 2007, 284 KB)
• AN 366: Understanding I/O Output Timing for Altera Devices (ver 1.0, Jul 2006, 311 KB)
• AN 409: Design Example Using the altlvds Megafunction & the External PLL Option in Stratix II Devices (ver 1.0, Mar 2006, 244 KB)
Design Example ( 7 MB)
• AN 411: Understanding PLL Timing for Stratix II Devices (ver 1.0, Mar 2006, 1 MB)
Design Example 1 ( 279 KB)
Design Example 2 ( 233 KB)
• AN 325: Interfacing RLDRAM II with Stratix II, Stratix & Stratix GX Devices (ver 3.1, Nov 2005, 2 MB)
• AN 393: Stratix II Professional Filtering Lab (ver 1.0, Aug 2005, 1 MB)
• AN 394: Using SOPC Builder & DSP Builder Tool Flow (ver 1.0, Aug 2005, 910 KB)
• AN 395: Stratix II Professional FFT Co-Processor Reference Design (ver 1.0, Aug 2005, 446 KB)
• AN 384: Using Calibrated Series On-Chip Termination in Stratix II Devices (ver 1.0, Apr 2005, 116 KB)
User-Mode Calibration Reference Design (Quartus II Version 4.2 SP1) ( 233 KB)
User-Mode Calibration Reference Design (Quartus II Version 5.0) ( 233 KB)
• AN 379: Active Serial Memory Interface Controller Reference Design (ver 1.0, Mar 2005, 191 KB)
Design Files ( 11 KB)
• AN 360: Updating Simulation Models for the POS-PHY Level 4 MegaCore Function (ver 1.1, Dec 2004, 63 KB)
• AN 306: Implementing Multipliers in FPGA Devices (ver 3.0, Jul 2004, 733 KB)
• AN 355: Stratix II Device System Power Considerations (ver 1.0, Jun 2004, 274 KB)
• AN 315: Guidelines for Designing High-Speed FPGA PCBs (ver 1.1, Feb 2004, 2 MB)

White Papers

• Basic Principles of Signal Integrity (ver 1.3, Dec 2007, 548 KB)
• Implementation of the Smith-Waterman Algorithm on a Reconfigurable Supercomputing Platform (ver 1.0, Sep 2007, 1 MB)
• FPGA Performance Benchmarking Methodology (ver 1.6, Aug 2007, 246 KB)
• SEmulation: Turbocharging the FPGA Development Process (ver 1.0, Mar 2007, 1 MB)
• Stratix II Performance and Logic Efficiency Analysis (ver 2.0, Sep 2006, 1 MB)
• Stratix II vs. Virtex-4 Performance Comparison (ver 2.0, Sep 2006, 505 KB)
• Stratix II DDR2 System Validation Summary (ver 1.0, May 2006, 1 MB)
• Architectural Differences Between Stratix II & Stratix Devices (ver 1.1, Jan 2006, 324 KB)
• Versatile Digital QAM Modulator (ver 1.1, Jan 2006, 586 KB)
• Stratix II vs. Virtex-4 Density Comparison (ver 2.2, Aug 2005, 264 KB)
• Stratix II vs. Virtex-4 Power Comparison & Estimation Accuracy (ver 1.0, Aug 2005, 356 KB)
• Input Signal Edge Rate Guidance (ver 1.0, Jun 2005, 63 KB)
• FPGAs for High-Performance DSP Applications (ver 1.1, May 2005, 119 KB)
• Using Parity to Detect Memory Errors in Stratix Devices (ver 1.2, Feb 2005, 97 KB)
• Stratix II DSP Performance (ver 2.0, Jan 2005, 241 KB)
• Stratix vs. Virtex-II Pro FPGA Performance Analysis (ver 1.1, Nov 2004, 146 KB)
• Benefits of Altera's High-Speed DDR2 SDRAM Memory Interface Solution (ver 1.0, May 2004, 273 KB)
• Implementing a Queue Manager in Traffic Management Systems (ver 1.1, Feb 2004, 125 KB)
• The Need for Dynamic Phase Alignment in High-Speed FPGAs (ver 1.1, Feb 2004, 71 KB)
• Altera Hot-Socketing & Power-Sequencing Advantages (ver 1.2, Feb 2004, 79 KB)
• MorphIO: An I/O Reconfiguration Solution for Altera Devices (ver 1.0, May 2003, 46 KB)
Tcl File ( 5 KB)
Readme File ( 7 KB)

Selector Guides

• Altera Product Catalog (ver 7.1, Nov 2009, 815 KB)
• Stratix FPGA Series Package & I/O Matrix (ver 1.0, Aug 2006, 75 KB)

Errata Sheets

• Stratix II FPGA Family Errata Sheet (ver 2.1, Oct 2008, 224 KB)
• DSP Development Kit, Stratix II Edition Errata Sheet v1.1 (ver 1.0, Sep 2005, 97 KB)
• DSP Development Kit, Stratix II Edition Errata Sheet (ver 1.0, Apr 2005, 88 KB)
• High Speed Development Kit, Stratix II Edition Errata Sheet (ver 1.0, Apr 2005, 69 KB)

Technical Briefs

• TB 086: Stratix II Military Temperature Range Support (ver 2.0, Oct 2007, 34 KB)
• TB 091: External Memory Interface Options for Stratix II Devices (ver 1.2, Mar 2007, 581 KB)

Application Briefs

• Understanding FLEX 8000 Timing (ver 1.0, Jun 2005, 96 KB)

Product Overview

• Altera Enhanced COTS PLD Initiative (ver 1.1, Jul 2008, 122 KB)
• Altera wireless solutions - 3GPP Long-Term Evolution (ver 1.0, Jan 2008, 68 KB)
• Broadband access solutions from Altera (ver 1.0, Sep 2007, 263 KB)
• Accelerating applications on coprocessing platforms (ver 1.0, Jul 2007, 104 KB)
• Industrial Snakebytes sell sheet (ver 1.0, Apr 2007, 112 KB)
• Complete Memory Interface Design Solutions (ver 1.0, Sep 2006, 149 KB)

Process Change Notifications

• PCN 0902 Additional Assembly Source and Bill of Material Change for Altera Flip Chip Products (Apr 2009, 591 KB)

Inserts and Advertorials

• Protecting IP Through FPGA Design Security (ver 1.0, Oct 2006, 933 KB)
  (advertorial)