Evolutions in technology are improving beyond traditional programmable digital signal processing (DSP) device capabilities. The degree of flexibility offered by programmable logic and the associated throughput benefits make FPGAs and PLDs increasingly attractive alternatives for performance-hungry applications.
In modern multi-channel systems, where similar data arrives at very high sampling rates and is subject to simultaneous algorithmic transformations, FPGA implementations with high I/O rates and parallel structures provide a tangible benefit at a fraction of the cost of a multi-processor-based DSP approach.
Altera’s set of DSP documentation presents the design flow commonly used in the FPGA design community. To view all DSP literature, click the link below.
DSP Literature (November 2009) (95 MB)
I. DSP Design Building Blocks
FFT MegaCore Function User Guide (ver 9.1, Nov 2009, 1 MB) - CIC MegaCore Function User Guide (ver 9.1, Nov 2009, 780 KB)
- NCO MegaCore Function User Guide (ver 9.1, Nov 2009, 968 KB)
- FIR Compiler User Guide (ver 9.1, Nov 2009, 2 MB)
- Reed-Solomon Compiler User Guide (ver 9.1, Nov 2009, 642 KB)
- Viterbi Compiler User Guide (ver 9.1, Nov 2009, 991 KB)
- Video and Image Processing Suite User Guide (ver 9.1, Nov 2009, 6 MB)
- AN 404: FFT/IFFT Block Floating Point Scaling (ver 1.0, Oct 2005, 110 KB)
- AN 455: Understanding CIC Compensation Filters (ver 1.0, Apr 2007, 268 KB)
- DSP Builder Installation and Licensing (ver 9.0, Mar 2009, 245 KB)
- DSP Builder User Guide (ver 9.1, Nov 2009, 13 MB)
- DSP Builder Reference Manual (ver 9.1 SP1, Feb 2010, 12 MB)
- DSP Builder Release Notes and Errata (ver 5.0, Nov 2009, 146 KB)
- DSP Design Flow User Guide (ver 3.3, Nov 2009, 603 KB)
- DSP Builder Advanced Blockset User Guide (ver 9.1 SP1, Feb 2010, 5 MB)
- DSP Builder Advanced Blockset Reference Manual (ver 9.1 SP1, Feb 2009, 1 MB)
- DSP Development Kit Getting Started User Guide (ver 1.0, Oct 2008, 2 MB)
- DSP Development Kit, Stratix & Stratix Professional Edition Getting Started User Guide (ver 1.3.0 rev 1, Dec 2004, 2 MB)
- DSP Development Kit, Cyclone II Edition Getting Started User Guide (ver 1.1, Sep 2007, 3 MB)
(RoHS compliant) - Stratix EP1S80 DSP Development Board Data Sheet (ver 1.3, Dec 2004, 1 MB)
- Stratix EP1S25 DSP Development Board Data Sheet (ver 1.6, Dec 2004, 663 KB)
- Cyclone II DSP Development Board Reference Manual (ver 1.1, Sep 2007, 2 MB)
(RoHS compliant) - Stratix II EP2S180 DSP Development Board Reference Manual (ver 1.0, Aug 2005, 549 KB)
- Stratix II DSP Development Board Reference Manual (ver 6.0.1, Aug 2006, 447 KB)
- DSP Blocks in Stratix & Stratix GX Devices (ver 2.2, Jul 2005, 267 KB)
(Replaces AN 214) - Implementing High-Performance DSP Functions in Stratix & Stratix GX Devices (ver 1.1, Sep 2004, 760 KB)
(Replaces AN 215) - DSP Blocks in Stratix II & Stratix II GX Devices (ver 2.2, Jan 2008, 339 KB)
- Stratix II DSP Performance (ver 2.0, Jan 2005, 241 KB)
- DSP Blocks in Stratix III Devices (ver 1.6, May 2009, 446 KB)
- DSP Blocks in Stratix IV Devices (ver 3.0, Nov 2009, 1 MB)
- DSP Blocks in Arria GX Devices (ver 1.2, May 2008, 322 KB)
- DSP Blocks in Arria II GX Devices (ver 2.0, Nov 2009, 907 KB)
- Embedded Multipliers in Cyclone II Devices (ver 1.2, Feb 2007, 152 KB)
- Embedded Multipliers in Cyclone III Devices (ver 2.1, Jul 2009, 141 KB)
- Embedded Multipliers in Cyclone IV Devices (ver 1.0, Nov 2009, 161 KB)
- DSP Block Implementation in HardCopy III Devices (ver 2.0, Dec 2008, 105 KB)
- DSP Block Implementation in HardCopy IV Devices (ver 1.0, Dec 2008, 104 KB)
- FPGAs for High-Performance DSP Applications (ver 1.1, May 2005, 119 KB)
- Implementing FFT in an FPGA Co-Processor (ver 1.0, Mar 2005, 1 MB)
(presented at GSPx) - Adaptive Edge Detection for Real-Time Video Processing using FPGAs (ver 1.0, Mar 2005, 341 KB)
(presented at GSPx) - Direct Up-Conversion using an FPGA-based Polyphase Modem (ver 1.0, Mar 2005, 240 KB)
(presented at GSPx) - Extending the Peripheral Set of DSP Processors using FPGAs (ver 1.0, Mar 2005, 1 MB)
(presented at GSPx) - Rapid FPGA Modem Design Techniques for SDRs using Altera DSP Builder (ver 1.0, Mar 2005, 1 MB)
(presented at GSPx) - FPGA Co-Processing Solutions for High Performance Signal Processing Applications (ver 1.0, Mar 2005, 318 KB)
(presented at GSPx) - Studies on FIR Filter Pre-Emphasis for High-Speed Backplane Data Transmission (ver 1.0, Mar 2005, 2 MB)
(presented at GSPx) - Enabling Real-Time JPEG2000 with FPGA Architectures (ver 1.0, Mar 2005, 2 MB)
(presented at GSPx) - A Simple Data Pre-Distortion Technique for Satellite Communications (ver 1.0, Mar 2005, 2 MB)
(presented at GSPx) - Soft Multipliers For DSP Applications (ver 1.0, May 2003, 490 KB)
- AN 306: Implementing Multipliers in FPGA Devices (ver 3.0, Jul 2004, 733 KB)
- Versatile Digital QAM Modulator (ver 1.1, Jan 2006, 586 KB)
- Increase Bandwidth in Medical & Industrial Applications With FPGA Co-Processors (ver 2.1, Feb 2006, 494 KB)
- Implementation of CORDIC-Based QRD-RLS Algorithm on Altera Stratix FPGA with Embedded Nios Soft Processor Technology (ver 1.0, Mar 2004, 119 KB)
- AN 245: Filtering Reference Design Lab (ver 3.0, Dec 2004, 670 KB)
- AN 263: CORDIC Reference Design (ver 1.4, Jun 2005, 323 KB)
- AN 314: Digital Predistortion Reference Design (ver 1.0, Jul 2003, 1 MB)
- AN 317: Turbo Encoder Co-processor Reference Design (ver 1.2, Oct 2003, 183 KB)
- AN 332: Link-Port Reference Design (ver 1.3, Feb 2005, 1 MB)
- AN 334: ADI Parallel Port SDRAM Controller Reference Design (ver 1.3, Jun 2005, 753 KB)
- AN 339: Serial Digital Interface Demonstration for Stratix II GX Devices (ver 3.3, May 2007, 288 KB)
- AN 347: Farrow-Based Decimating Sample Rate Converter (ver 1.0, Mar 2004, 256 KB)
- AN 362: Stratix II Filtering Lab (ver 1.0, Oct 2004, 1 MB)
- AN 363: FFT Co-Processor Reference Design (ver 1.0, Oct 2004, 1 MB)
- AN 364: Edge Detection Reference Design (ver 1.0, Oct 2004, 1 MB)
- AN 371: Automotive Graphics System Reference Design (ver 1.0, Dec 2004, 195 KB)
- AN 375: Cyclone II FFT Co-Processor Reference Design (ver 1.0, May 2005, 566 KB)
- AN 376: Cyclone II Filtering Lab (ver 1.0, May 2005, 1 MB)
- AN 383: Cyclone II DDR2 SDRAM Demonstration (ver 1.0, Apr 2005, 175 KB)
- AN 388: High-Performance EMIF Bridge Core (ver 1.2, Sep 2005, 435 KB)
- AN 393: Stratix II Professional Filtering Lab (ver 1.0, Aug 2005, 1 MB)
- AN 412: A Scalable OFDMA Engine for WiMAX (ver 2.1, May 2007, 359 KB)
- AN 421: Accelerating WiMAX DUC & DDC System Designs (ver 2.2, May 2007, 758 KB)
- AN 427: Video and Image Processing Example Design (ver 8.0, Nov 2009, 3 MB)
- AN 430: WiMAX OFDMA Ranging (ver 1.0, Aug 2006, 769 KB)
- AN 434: Channel Estimation & Equalization for Mobile WiMAX Basestations (ver 1.1, May 2007, 748 KB)
- AN 439: Constellation Mapper and Demapper for WiMAX (ver 1.1, May 2007, 250 KB)
- AN 442: Tool Flow for Design of Digital IF for Wireless Systems (ver 1.0, May 2007, 1 MB)
- AN 450: Uplink Desubchannelization for WiMAX (ver 1.0, Feb 2007, 319 KB)
- AN 451: Downlink Subchannelization for WiMAX (ver 1.0, Feb 2007, 319 KB)
- AN 452: An OFDM Kernel for WiMAX (ver 1.0, Feb 2007, 319 KB)
- AN 475: Crest Factor Reduction for OFDMA Systems (ver 1.0, Dec 2007, 362 KB)
- AN 480: 1536-Point FFT for 3GPP Long Term Evolution (ver 1.0, Oct 2007, 154 KB)
- AN 504: DSP System Design in Stratix III Devices (ver 1.0, Feb 2008, 1 MB)
- Design Example 1: Parallel FIR
- Design Example 2: Multi-Channel FIR
- Design Example 3: MAC_FIR (vhdl)
- Design Example 4: Large Mult_Add
- AN 506: QR Matrix Decomposition (ver 2.0, Mar 2008, 371 KB)
- AN 515: 24K FFT for 3GPP LTE RACH Detection (ver 1.0, Nov 2008, 230 KB)
- AN 544: Digital IF Modem Design with the DSP Builder Advanced Blockset (ver 1.0, Aug 2008, 976 KB)
For a complete list of errata sheets, see www.altera.com/literature/lit-es.jsp.
