Literature: DSP
Evolutions in technology are improving beyond traditional programmable digital signal processing (DSP) device capabilities. The degree of flexibility offered by programmable logic and the associated throughput benefits make FPGAs and PLDs increasingly attractive alternatives for performance-hungry applications.
In modern multi-channel systems, where similar data arrives at very high sampling rates and is subject to simultaneous algorithmic transformations, FPGA implementations with high I/O rates and parallel structures provide a tangible benefit at a fraction of the cost of a multi-processor-based DSP approach.
Altera’s set of DSP documentation presents the design flow commonly used in the FPGA design community. To view all DSP literature, click the link below.
I. DSP Design Building Blocks
- FFT MegaCore Function User Guide (ver 7.2, Oct 2007, 946 KB)
- CIC MegaCore Function User Guide (ver 7.2, Oct 2007, 595 KB)
- NCO MegaCore Function User Guide (ver 7.2, Oct 2007, 974 KB)
- FIR Compiler User Guide (ver 7.2, Oct 2007, 3,004 KB)
- Reed-Solomon Compiler User Guide (ver 7.2, Oct 2007, 687 KB)
- Viterbi Compiler User Guide (ver 7.2, Oct 2007, 703 KB)
- Video and Image Processing Suite User Guide (ver 7.2, Oct 2007, 2,308 KB)
- AN 404: FFT/IFFT Block Floating Point Scaling (ver 1.0, Oct 2005, 110 KB)
- AN 455: Understanding CIC Compensation Filters (ver 1.0, Apr 2007, 267 KB)
II. DSP Development Flow – DSP/SOPC Builder
- DSP Builder User Guide (ver 7.2.1, Dec 2007, 8,294 KB)
- DSP Builder Reference Manual (ver 7.2.1, Dec 2007, 4,650 KB)
- DSP Builder Release Notes and Errata (ver 1.2, Dec 2007, 308 KB)
- FPGAs Provide Reconfigurable DSP Solutions (ver 1.0, Aug 2002, 216 KB)
III. Hardware Development
- DSP Development Kit, Stratix II Edition Getting Started User Guide (ver 1.1, May 2005, 645 KB)
- DSP Development Kit, Stratix & Stratix Professional Edition Getting Started User Guide (ver 1.3.0 rev 1, Dec 2004, 1,994 KB)
- DSP Development Kit, Cyclone II Edition Getting Started User Guide (ver 1.1, Sep 2007, 3,002 KB)
(RoHS compliant)
- Stratix II EP2S60 DSP Development Board Data Sheet (ver 1.1, May 2005, 515 KB)
- Stratix EP1S80 DSP Development Board Data Sheet (ver 1.3, Dec 2004, 1,297 KB)
- Stratix EP1S25 DSP Development Board Data Sheet (ver 1.6, Dec 2004, 663 KB)
- Cyclone II DSP Development Board Reference Manual (ver 1.1, Sep 2007, 1,721 KB)
(RoHS compliant)
- Stratix II EP2S180 DSP Development Board Reference Manual (ver 1.0, Aug 2005, 548 KB)
IV. Device Selection and Architecture
- DSP Blocks in Stratix & Stratix GX Devices (ver 2.2, Jul 2005, 266 KB)
(Replaces AN 214)
- Implementing High-Performance DSP Functions in Stratix & Stratix GX Devices (ver 1.1, Sep 2004, 760 KB)
(Replaces AN 215)
- DSP Blocks in Stratix II & Stratix II GX Devices (ver 2.1, Feb 2007, 327 KB)
- DSP Blocks in Stratix III Devices (ver 1.2, Oct 2007, 339 KB)
- Stratix II DSP Performance (ver 2.0, Jan 2005, 240 KB)
- Embedded Multipliers in Cyclone II Devices (ver 1.2, Feb 2007, 152 KB)
- DSP Blocks in Arria GX Devices (ver 1.1, Aug 2007, 307 KB)
V. DSP Applications Using FPGAs
- FPGAs for High-Performance DSP Applications (ver 1.1, May 2005, 118 KB)
- Implementing FFT in an FPGA Co-Processor (ver 1.0, Mar 2005, 1,448 KB)
(presented at GSPx)
- Adaptive Edge Detection for Real-Time Video Processing using FPGAs (ver 1.0, Mar 2005, 340 KB)
(presented at GSPx)
- Direct Up-Conversion using an FPGA-based Polyphase Modem (ver 1.0, Mar 2005, 240 KB)
(presented at GSPx)
- Extending the Peripheral Set of DSP Processors using FPGAs (ver 1.0, Mar 2005, 1,450 KB)
(presented at GSPx)
- Rapid FPGA Modem Design Techniques for SDRs using Altera DSP Builder (ver 1.0, Mar 2005, 1,437 KB)
(presented at GSPx)
- FPGA Co-Processing Solutions for High Performance Signal Processing Applications (ver 1.0, Mar 2005, 317 KB)
(presented at GSPx)
- Studies on FIR Filter Pre-Emphasis for High-Speed Backplane Data Transmission (ver 1.0, Mar 2005, 1,581 KB)
(presented at GSPx)
- Enabling Real-Time JPEG2000 with FPGA Architectures (ver 1.0, Mar 2005, 1,731 KB)
(presented at GSPx)
- A Simple Data Pre-Distortion Technique for Satellite Communications (ver 1.0, Mar 2005, 1,762 KB)
(presented at GSPx)
- Soft Multipliers For DSP Applications (ver 1.0, May 2003, 490 KB)
- AN 306: Implementing Multipliers in FPGA Devices (ver 3.0, Jul 2004, 732 KB)
- Versatile Digital QAM Modulator (ver 1.1, Jan 2006, 585 KB)
- Increase Bandwidth in Medical & Industrial Applications With FPGA Co-Processors (ver 2.1, Feb 2006, 493 KB)
- Implementation of CORDIC-Based QRD-RLS Algorithm on Altera Stratix FPGA with Embedded Nios Soft Processor Technology (ver 1.0, Mar 2004, 118 KB)
VI. Reference Designs
- AN 245: Filtering Reference Design Lab (ver 3.0, Dec 2004, 669 KB)
- AN 263: CORDIC Reference Design (ver 1.4, Jun 2005, 323 KB)
- AN 314: Digital Predistortion Reference Design (ver 1.0, Jul 2003, 1,380 KB)
- AN 317: Turbo Encoder Co-processor Reference Design (ver 1.2, Oct 2003, 183 KB)
- AN 332: Link-Port Reference Design (ver 1.3, Feb 2005, 1,409 KB)
- AN 334: ADI Parallel Port SDRAM Controller Reference Design (ver 1.3, Jun 2005, 752 KB)
- AN 339: Serial Digital Interface Demonstration for Stratix II GX Devices (ver 3.3, May 2007, 288 KB)
- AN 347: Farrow-Based Decimating Sample Rate Converter (ver 1.0, Mar 2004, 255 KB)
- AN 357: Error Detection & Recovery Using CRC in Altera FPGA Devices (ver 1.3, Feb 2007, 178 KB)
- AN 362: Stratix II Filtering Lab (ver 1.0, Oct 2004, 1,121 KB)
- AN 363: FFT Co-Processor Reference Design (ver 1.0, Oct 2004, 1,228 KB)
- AN 364: Edge Detection Reference Design (ver 1.0, Oct 2004, 1,498 KB)
- AN 371: Automotive Graphics System Reference Design (ver 1.0, Dec 2004, 194 KB)
- AN 375: Cyclone II FFT Co-Processor Reference Design (ver 1.0, May 2005, 566 KB)
- AN 376: Cyclone II Filtering Lab (ver 1.0, May 2005, 1,147 KB)
- AN 377: Edge Detection Using SOPC Builder & DSP Builder Tool Flow (ver 1.0, May 2005, 1,321 KB)
- AN 383: Cyclone II DDR2 SDRAM Demonstration (ver 1.0, Apr 2005, 174 KB)
- AN 388: High-Performance EMIF Bridge Core (ver 1.2, Sep 2005, 434 KB)
- AN 393: Stratix II Professional Filtering Lab (ver 1.0, Aug 2005, 1,224 KB)
- AN 412: A Scalable OFDMA Engine for WiMAX (ver 2.1, May 2007, 359 KB)
- AN 421: Accelerating WiMAX DUC & DDC System Designs (ver 2.2, May 2007, 758 KB)
- AN 427: Video and Image Processing Up Conversion Example Design (ver 4.0, Oct 2007, 1,621 KB)
- AN 430: OFDMA WiMAX Ranging (ver 1.0, Aug 2006, 769 KB)
- AN 434: Channel Estimation & Equalization for Mobile WiMAX Basestations (ver 1.1, May 2007, 747 KB)
- AN 439: Constellation Mapper and Demapper for WiMAX (ver 1.1, May 2007, 250 KB)
- AN 442: Tool Flow for Design of Digital IF for Wireless Systems (ver 1.0, May 2007, 1,394 KB)
- AN 450: Uplink Desubchannelization for WiMAX (ver 1.0, Feb 2007, 318 KB)
- AN 451: Downlink Subchannelization for WiMAX (ver 1.0, Feb 2007, 318 KB)
- AN 452: An OFDM Kernel for WiMAX (ver 1.0, Feb 2007, 319 KB)
- AN 475: Crest Factor Reduction for OFDMA Systems (ver 1.0, Dec 2007, 361 KB)
- AN 480: 1536-Point FFT for 3GPP Long Term Evolution (ver 1.0, Oct 2007, 153 KB)
- AN 504: DSP System Design in Stratix III Devices (ver 1.0, Feb 2008, 1,053 KB)
- AN 506: QR Matrix Decomposition (ver 2.0, Mar 2008, 371 KB)
VII. Errata Sheets
For a complete list of errata sheets, see www.altera.com/literature/lit-es.jsp.
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