// Copyright (C) 1991-2007 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, Altera MegaCore Function License 
// Agreement, or other applicable license agreement, including, 
// without limitation, that your use is for the sole purpose of 
// programming logic devices manufactured by Altera and sold by 
// Altera or its authorized distributors.  Please refer to the 
// applicable agreement for further details.

// *****************************************************************************
// This file contains a Verilog test bench with test vectors .The test vectors  
// are exported from a vector file in the Quartus Waveform Editor and apply to  
// the top level entity of the current Quartus project .The user can use this   
// testbench to simulate his design using a third-party simulation tool .       
// *****************************************************************************
// Generated on "05/02/2007 15:39:51"
                                                                        
// Verilog Self-Checking Test Bench (with test vectors) for design :    counter_example
// 
// Simulation tool : 3rd Party
// 

`timescale 1 ps/ 1 ps
module counter_example_vlg_sample_tst(
	clock,
	reset,
	sampler_tx
);
input  clock;
input  reset;
output sampler_tx;

reg sample ;

always @(clock or reset)
                                                                                
begin                                         
 if ($time > 0)                               
 begin                                        
     if (sample === 1'bx)                     
	sample = 0;                           
     else                                     
        sample = ~sample;                     
 end                                          
end                                           

assign sampler_tx = sample;
endmodule

module counter_example_vlg_check_tst (
	cout,sampler_rx
);
input [8:0] cout;
input sampler_rx;

reg [8:0] cout_expected;

reg [8:0] cout_prev;

reg [8:0] cout_expected_prev;

reg [8:0] last_cout_exp;

reg trigger;

integer i;
integer nummismatches;

reg [1:1] on_first_change ;


initial
begin
trigger = 0;
i = 0;
nummismatches = 0;
on_first_change = 1'b1;
end

// update real /o prevs

always @(trigger)
begin
	cout_prev = cout;
end

// update expected /o prevs

always @(trigger)
begin
	cout_expected_prev = cout_expected;
end


// expected cout[ 8 ]
initial
begin
	cout_expected[8] = 1'b0;
end 
// expected cout[ 7 ]
initial
begin
	cout_expected[7] = 1'b0;
end 
// expected cout[ 6 ]
initial
begin
	cout_expected[6] = 1'b0;
end 
// expected cout[ 5 ]
initial
begin
	cout_expected[5] = 1'b0;
end 
// expected cout[ 4 ]
initial
begin
	cout_expected[4] = 1'b0;
end 
// expected cout[ 3 ]
initial
begin
	cout_expected[3] = 1'b0;
	cout_expected[3] = #52500 1'b1;
	cout_expected[3] = #6700 1'b0;
end 
// expected cout[ 2 ]
initial
begin
	cout_expected[2] = 1'b0;
	cout_expected[2] = #32500 1'b1;
	cout_expected[2] = #20000 1'b0;
	cout_expected[2] = #40000 1'b1;
end 
// expected cout[ 1 ]
initial
begin
	cout_expected[1] = 1'b0;
	cout_expected[1] = #22500 1'b1;
	cout_expected[1] = #10000 1'b0;
	cout_expected[1] = #10000 1'b1;
	cout_expected[1] = #10000 1'b0;
	cout_expected[1] = #30000 1'b1;
	cout_expected[1] = #10000 1'b0;
	cout_expected[1] = #10000 1'b1;
end 
// expected cout[ 0 ]
initial
begin
	cout_expected[0] = 1'b0;
	# 17500;
	repeat(4)
	begin
		cout_expected[0] = 1'b1;
		cout_expected[0] = #5000 1'b0;
		# 5000;
	end
	cout_expected[0] = 1'b1;
	cout_expected[0] = #1700 1'b0;
	# 18300;
	repeat(3)
	begin
		cout_expected[0] = 1'b1;
		cout_expected[0] = #5000 1'b0;
		# 5000;
	end
	cout_expected[0] = 1'b1;
end 
// generate trigger
always @(cout_expected or cout)
begin
	trigger <= ~trigger;
end

always @(posedge sampler_rx or negedge sampler_rx)
begin
`ifdef debug_tbench
	$display("Scanning pattern %d @time = %t",i,$realtime );
	i = i + 1;
	$display("| expected cout = %b | ",cout_expected_prev);
	$display("| real cout = %b | ",cout_prev);
`endif
	if (
		( cout_expected_prev !== 9'bx ) && ( cout_prev !== cout_expected_prev )
		&& ((cout_expected_prev !== last_cout_exp) ||
			on_first_change[1])
	)
	begin
		$display ("ERROR! Vector Mismatch for output port cout :: @time = %t,Expected value = %b ; Real value = %b", $realtime, cout_expected_prev, cout_prev);
		nummismatches = nummismatches + 1;
		on_first_change[1] = 1'b0;
		last_cout_exp = cout_expected_prev;
	end

	trigger <= ~trigger;
end
initial 

begin 
$timeformat(-12,3," ps",6);
#110000;
if (nummismatches > 0)
	$display ("%d mismatched vectors : Simulation failed !",nummismatches);
else
	$display ("Simulation passed !");
$stop;
end 
endmodule

module counter_example_vlg_vec_tst();
// constants                                           
// general purpose registers
reg clock;
reg reset;
// wires                                               
wire [8:0] cout;

wire sampler;                             

// assign statements (if any)                          
counter_example i1 (
// port map - connection between master ports and signals/registers   
	.clock(clock),
	.cout(cout),
	.reset(reset)
);

// clock
always
begin
	clock = 1'b0;
	clock = #2500 1'b1;
	#2500;
end 

// reset
initial
begin
	reset = 1'b0;
	reset = #50 1'b1;
	reset = #14300 1'b0;
	reset = #44850 1'b1;
	reset = #16600 1'b0;
end 

counter_example_vlg_sample_tst tb_sample (
	.clock(clock),
	.reset(reset),
	.sampler_tx(sampler)
);

counter_example_vlg_check_tst tb_out(
	.cout(cout),
	.sampler_rx(sampler)
);
endmodule