4.1 4.2.2 - The models are designated as "Correlated" and have been correlated against physical device option. 2.6 Derived from stratix3_spice_model, rev 1.1, dated 29/06/07 using HSPICE Y-2006.03 - v2.6 - Added expanded OCT Rs range IBIS models with series OCT 40 Ohm with calibration and series OCT 60 Ohm with calibration - Update the keyword values - Updated the IBIS models of 2.5V LVDS, 2.5V mini-LVDS and 2.5V RSDS I/O standards with zero pre-emphasis setting - v2.5 - Added pseudo LVDS, RSDS and mini-LVDS 3 resistors network IBIS models with slew rate s0, s1 and s3 - Updated the notes section - Updated the status of the IBIS Models to "Correlated" - Updated C_comp values for all models except lvpecl25_rin from C_comp 4.0pF 4.0pF 4.0pF to C_comp 2.5pF 2.5pF 2.5pF - Updated C_comp values for lvpecl25_rin from C_comp 4.0pF 4.0pF 4.0pF to C_comp 0.4pF 0.4pF 0.4pF - Updated the following ibis models: - ttl18_rrio_r50c - ttl25_rtio_r50c - v2.4 - Updated signal_name in [Pin] section for the following I/O standard: - 2.5V LVDS - 2.5V Mini-LVDS - 2.5V RSDS - Updated the following ibis models: - lvds25_co_e3r_s2 - mlvds25_co_e3r_s2 - rsds25_co_e3r_s2 - v2.3 - Updated Model Spec values for 1.8V SSTL and Differential 1.8V SSTL: - changes: - [Model Spec] to [Model Spec] - Vinh 1.15 1.078 1.204 Vinh 1.15 1.083 1.219 - Vinl 0.65 0.578 0.704 Vinl 0.65 0.583 0.719 - Added IBIS models with series OCT with calibration and parallel OCT with calibration - Updated Vinl and Vinh value for the following I/O standard: - 3.0V PCI-X Vinl = 0.9V to Vinl = 1.05V - 2.5V Mini-LVDS Vinl = 1.2V to Vinl = 1.15V - 2.5V Mini-LVDS Vinh = 1.3V to Vinh = 1.35V - 2.5V LVPECL Vinl = 1.2V to Vinl = 1.1V - 2.5V LVPECL Vinh = 1.3V to Vinh = 1.4V - Updated vdiff value for the following I/O standard - 2.5V Mini-LVDS - vdiff = 0.1V to vdiff = 0.2V - 2.5V LVPECL - vdiff = 0.1V to vdiff = 0.3V - Differential 1.5V SSTL - vdiff = 0.4V to vdiff = 0.35V - Differential 2.5V SSTL - vdiff = 0.6V to vdiff = 0.62V - v2.2 - Updated Vmeas value for the following I/O standard: - 3.3V LVTTL - Vmeas = 1.425V to Vmeas = 1.5675V - 3.3V LVCMOS - Vmeas = 1.425V to Vmeas = 1.5675V - 2.5V LVDS25 - Vmeas = 1.1875V to Vmeas = 1.1625V - 2.5V mini-LVDS25 - Vmeas = 1.1875V to Vmeas = 1.1625V - 2.5V RSDS25 - Vmeas = 1.1875V to Vmeas = 1.1625V - Updated Vinl,Vinh and Model Spec values for the following models: - sstl15c1_rrio_r50 - sstl15c1_rtio_r50 - sstl15c1_cio_r50 - sstl15c2_cio_r50 - changes: - Vinl = 0.55 to Vinl = 0.575 - Vinh = 0.95 to Vinh = 0.925 - [Model Spec] to [Model Spec] - Vinh 0.95 0.88 1.1 Vinh 0.925 0.88 0.97 - Vinl 0.55 0.48 0.7 Vinl 0.575 0.53 0.62 - Updated Vinl,Vinh and Model Spec values for the following models: - sstl18c1_rrio_r50 - sstl18c1_rtio_r50 - sstl18c2_rtio_r25 - sstl18c1_cio_r50 - sstl18c2_cio_r25 - changes: - Vinl = 0.7 to Vinl = 0.65 - Vinh = 1.1 to Vinh = 1.15 - [Model Spec] to [Model Spec] - Vinh 1.1 1.05 1.15 Vinh 1.15 1.078 1.204 - Vinl 0.7 0.65 0.75 Vinl 0.65 0.578 0.704 - Updated Vinl,Vinh and Model Spec values for the following model: - hstl18c2_rrio_r25 - changes: - Vinl = 0.65 to Vinl = 0.7 - Vinh = 1.15 to Vinh = 1.1 - [Model Spec] to [Model Spec] - Vinh 1.15 1.078 1.204 Vinh 1.1 1.05 1.15 - Vinl 0.65 0.578 0.704 Vinl 0.7 0.65 0.75 - Updated temperature range values for some models of the following I/O standard: - 1.8V SSTL CI and CII - 1.8V DSSTL CI and CII - 2.5V SSTL CI and CII - 2.5V DSSTL CI and CII - Updated voltage range values for the input models of the following I/O standard: - 3.3V LVTTL - 3.3V LVCMOS - 1.2V HSTL and 1.2V DHSTL - 1.5V HSTL and 1.5V DHSTL - 1.8V HSTL and 1.8V DHSTL - 1.5V SSTL and 1.5V DSSTL - 1.8V SSTL and 1.8V DSSTL - 2.5V SSTL and 2.5V DSSTL - Updated voltage range values for 3.3V Configuration Models - Updated the following ibis models: - hstl15c1_rtio_d4s3 - dhstl15c1_rtio_d4s3 - lvds25_ro_p1_v2 - mlvds25_ro_p1_v2 - rsds25_ro_p1_v2 - v2.1 - Full corners release - Updated Vref and V_term1 value for the following I/O standard: - 1.8V HSTL CI and CII - Vref = 0.83V to Vref = 0.9V - 1.8V DHSTL CI and CII - Vref = 0.83V to Vref = 0.9V - 1.5V HSTL CI and CII - Vref = 0.6875V to Vref = 0.75V - 1.5V DHSTL CI and CII - Vref = 0.6875V to Vref = 0.75V - 1.2V HSTL CI and CII - Vref = 0.545V to Vref = 0.6V - 1.2V DHSTL CI and CII - Vref = 0.545V to Vref = 0.6V - SSTL-2 CI and CII - V_term1 = 1.1625V to V_term1 = 1.25V - DSSTL-2 CI and CII - V_term1 = 1.1625V to V_term1 = 1.25V - SSTL-18 CI and CII - V_term1 = 0.83V to V_term1 = 0.9V - DSSTL-18 CI and CII - V_term1 = 0.83V to V_term1 = 0.9V - SSTL-15 CI and CII - V_term1 = 0.6875V to V_term1 = 0.75V - DSSTL-15 CI and CII - V_term1 = 0.6875V to V_term1 = 0.75V - Updated DHSTL and DSSTL models with the following edits: - Model Type Output to Model Type I/O - Add Vinl and Vinh values - Add Model Spec keyword - Model names from co to cio, rro to rrio and rto to rtio - v2.0 - Initial Release (Typical conditions with default slew rate, pre-emphasis and VOD settings IBIS models) C_comp values for different pin types |When an IBIS model is assigned to different pin types in Stratix III |devices, the C_comp value will be different. Use the following C_comp |values according to the pin types: | |Pin Type C_comp |Normal I/O and dual purpose I/O 2.5pF |Dedicated clock input 0.4pF |Dual-purpose clock output/feedback pin 3.7pF |