APEX 20KE PLLs have 64% Less Jitter than Virtex-E DLLs
As programmable logic devices increase in density, on-chip clock management features such as clock delay and clock skew become important design considerations. To address these issues, designers may choose phase-locked loops (PLLs) or delay-locked loops (DLLs). Even though both technologies reduce the skew within the system, PLLs are more flexible than DLLs for frequency synthesis of system clocks providing full multiplication and division capabilities.
Another important feature for high-speed board designs is clock jitter. This specification is defined as a deviation from the ideal timing of clock transition events. Jitter can have a negative effect on a system's performance. For example, in high-speed data applications, the clock edge must occur during a very tight window of time to capture data correctly. Jitter causes the data to be outside the specified clock window, resulting in bit error because the data was captured incorrectly. Figure 1 shows an example of jitter.
Figure 1. Clock Jitter
Lab Experiment
A lab experiment was performed to measure jitter on the output of the APEX 20KE PLLs and Virtex-E DLLs. A 50-MHz, 4.0 ps low-jitter input clock was multiplied by using the 2x mode to create an output clock of 100 MHz. The output clock jitter of the PLL of an APEX 20KE device and the DLL of a Virtex-E device was measured using a LeCroy LC584AL 1-GHz scope. The lab experiment showed that APEX 20KE PLL has 64% less jitter than Virtex-E DLL.
Figure 2 shows the jitter distribution measured at the output of the APEX 20KE device and Virtex-E device.
Figure 2. APEX 20KE PLL vs. Virtex-E DLL Output Jitter Distribution
The peak-to-peak jitter specification for the APEX 20KE device is 210 ps, which is the 0.35% RMS value of the output clock period. For this particular frequency (100 MHz) the RMS jitter is 35 ps. To convert RMS value to peak-to-peak value we need to multiply by 6x. In this experiment, the peak-to-peak jitter for the APEX EP20K400E device was measured at 90 ps, well under the 210 ps specification. However, the peak-to-peak jitter for the Virtex-E XCV1000E device was measured at 250 ps, which is in violation of its own data sheet specification of ±60 ps cycle to cycle jitter.
The analog circuitry of the APEX 20KE PLL translates into a time-continuous transfer function. This transfer function acts as a filter on the PLL clock, attenuating high-frequency jitter. The discrete delay line architecture of a digital DLL is incapable of filtering the jitter of the input clock. For DLLs, the input jitter accumulates to the output. The Xilinx DLL output jitter specifications of ±60 ps is for zero-input DLL jitter. All input jitter is passed through to the output. For example, if the input clock has ±200 ps of jitter, the DLL output clock will have a jitter of ±260 ps.
Figure 3. APEX 20KE PLL vs. Virtex-E DLL Measured Output JitterResults
Conclusion
APEX PLLs, featuring the advanced ClockLock, ClockBoost, and ClockShift circuitry, provide significant improvements in system performance and design versatility by minimizing clock skew and clock delay. The flexible clock synthesis and robust clock shift capabilities of APEX PLLs provide for precise phase and delay adjustment. Designers can increase system performance by minimizing set up time and clock-to-output time (tSU and tCO ). PLLs allow support for high-performance I/O standards such as LVDS and provide the flexibility and capability unattainable by Virtex-E DLLs. Additionally, jitter on output of APEX 20KE PLL is 64% less than Virtex-E DLL, allowing for better system performance. With these advantages, APEX 20KE PLLs offer the best on-chip clock management solution today.
