Altera Home Page
Literature Licensing
Buy On-Line Download

  Home   |   Products   |   Support   |   End Markets   |   Technology Center   |   Education & Events   |   Corporate   |   Buy On-Line  
  Devices   |   Design Software   |   Intellectual Property   |   Design Services   |   Dev. Kits/Cables   |   Literature  

 High-End FPGAs
      About Stratix Series
   Stratix IV (E and GX)
   Stratix III (L and E)
   Stratix II (and GX)
   Stratix (and GX)
  
 Midrange FPGAs
   Arria (GX)
  
 Low-Cost FPGAs
   Cyclone III
   Cyclone II
   Cyclone
  
 CPLDs
   MAX II (and G, Z)
   MAX 3000A
  
 ASICs
      About HardCopy Series
   HardCopy IV (E and GX)
   HardCopy III
   HardCopy II
   HardCopy Stratix
  
 Device-Specific Offerings
   RoHS Compliant
      Extended Temperature
      Industrial Temperature
      Military Temperature
      Automotive Temperature
  
 Configuration Devices
   Enhanced Configuration
   Serial Configuration
  
 Mature Products
      Product Listing
  

APEX 20K Device Family Features

APEX logo APEX™ devices contain system-level features that offer design flexibility and system-integration functionality. Follow the links in Table 1 to find out more.

Table 1. APEX 20K Device Features at a Glance
Feature APEX 20K APEX 20KE APEX 20KC
True-LVDS circuitry   Full support Full support
MultiCore system integration Full support Full support Full support
Embedded system blocks (ESBs) for memory support Dual-port RAM
FIFO
RAM
ROM
CAM
Dual-port RAM
FIFO
RAM
ROM
CAM
Dual-port RAM
FIFO
RAM
ROM
Support for emerging I/O standards (1) 3.3-V PCI
LVCMOS
LVTTL
3.3-V PCI, PCI-X
AGP
CTT
GTL+
LVCMOS
LVDS
LVTTL
SSTL-2 Class I and II
SSTL-3 Class I and II
HSTL Class I
LVPECL
3.3-V PCI, PCI-X
AGP
CTT
GTL+
LVCMOS
LVDS
LVTTL
SSTL-2 Class I and II
SSTL-3 Class I and II
HSTL Class I
LVPECL
SignalTap® logic analysis Full support Full support Full support
Density up to 1.5 million gates (2.5 million maximum system gates) 100,000 to 400,000 gates 30,000 to 1,500,000 gates 200,000 to 1,500,000 gates
1.8-V and 2.5-V operation 2.5 V 1.8 V 1.8 V
Up to four phase-locked loops (PLLs) 1 PLL
Clock delay reduction
2x and 4x clock multiplication
Multiplication:
1x - 160x

Division:
1 - 256
Multiplication:
1x - 160x

Division:
1 - 256
MultiVolt I/O operation 5-V, 3.3-V &
2.5-V
3.3-V, 2.5-V & 1.8-V 3.3-V, 2.5-V & 1.8-V
FineLine BGA packaging Full Support Full support Full support
Vertical migration Full support Full support Full support
Advanced manufacturing process 0.25/0.22 µm 0.18 µm 0.15 µm, all-layer copper
HardCopy® ASIC availability for a cost reduction path to in high-volume production   Available Available

Note:

  1. AGP: advanced graphics port; CTT: center tap terminated; GTL+: gunning transceiver logic; HSTL: high-speed transceiver logic; LVCMOS: low-voltage complementary metal-oxide semiconductor; LVDS: low-voltage differential signaling; LVPECL: low-voltage positive emitter-coupled logic; LVTTL: low-voltage transistor-transistor logic; SSTL: stub-series terminated logic

Availability and Pricing

All APEX 20K, APEX 20KE, and APEX 20KC devices are shipping now. To check the availability and pricing of specific devices, contact your local Altera representative.

  Please Give Us Feedback