APEX High-Bandwidth I/O Interface Support
Altera's APEX devices support the emerging high-bandwidth I/O interface standards needed for today's demanding system requirements. Faster processors and memories are powering higher performance systems; process technology advancements are driving down supply voltage and power consumption. The emerging I/O standards supported by APEX devices are responding to these system changes with high-bandwidth, low-voltage operation and differential inputs to provide lower power consumption and less noise. Figure 1 shows some of the I/O interface solutions offered by APEX devices.
Figure 1. APEX Devices Support Emerging I/O Standards
APEX devices support a number of I/O standards, as shown in Table 1, including the unique
True-LVDS (low-voltage differential signaling) I/O standard. LVDS handles very high-speed data transfers at rates up to 840 Mbps per channel, which makes it ideal for applications such as point-to-point data links and backplane drivers. APEX devices can support up to 16 input and output LVDS channels, allowing for a programmable bandwidth of 26 Gbps.
| Table 1. I/O Standards Supported by APEX Devices |
| I/O Standard (1) |
Application |
| LVDS |
Backplane driver, fast ethernet, high-speed data links |
| GTL+ |
Processor interface, backplane driver |
| SSTL-2/3 |
Memory interface, fast SDRAM |
| 64-bit, 66-MHz PCI |
PCI bus interface |
| PCI-X |
PCI bus interface |
| AGP |
Graphics interface |
| LVCMOS |
General-purpose standard for 3.3-V applications |
| LVTTL |
General-purpose standard for 3.3-V applications |
| CTT |
General-purpose standard |
| HSTL |
High speed memory interface |
| LVPECL |
High performance clocking, backplanes,
optical transceiver, high speed networking |
Note:
1. GTL+: gunning transceiver logic; HSTL: high-speed transceiver logic; SSTL: stub-series terminated logic; PCI: peripheral component interconnect; AGP: advanced graphics port; LVCMOS: low-voltage complementary metal-oxide semiconductor; LVTTL: low-voltage transistor-transistor logic; CTT: center tap terminated; LVPECL: low-voltage positive emitter-coupled logic
Programmable I/O Banks
APEX I/O buffers meet the voltage, drive strength, and AC characteristics necessary for compliance with these I/O standards. APEX devices have eight programmable I/O banks, two of which can be used to support LVDS (see Figure 2). The programmable I/O banks have individual power planes with separate VCCIO pins for each I/O bank. The VCCIO plane supports 3.3-, 2.5-, and 1.8-V voltage levels.
Figure 2. APEX 20KE I/O Banks
APEX devices meets the American National Standards Institute/Telecommunication Industry Association/Electronics Industries Association standard 644 (ANSI/TIA/EIA-644). Two phase-locked loops (PLLs) on an APEX device can be used to provide frequency multiplication for LVDS.
Altera MultiVolt Interface
The Altera MultiVolt interface allows seamless incorporation of APEX devices on boards with varying voltage levels. The central interface device on a board--often a high-density programmable logic device (PLD)--must be able to connect with a mixture of 3.3-, 2.5- and 1.8-V devices. The MultiVolt feature makes APEX devices an excellent fit for this environment. In addition, APEX devices save board space and eliminate chip-to-chip delays by removing the requirement for an external transceiver.
The APEX I/O Interface Solution
Altera APEX devices meet the need for high-bandwidth I/O interface support with high-performance, low-voltage operation, low-power consumption, and low-noise operation. APEX devices offer designers the ideal I/O standard support for high-performance designs.
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