APEX Phase-Locked Loop Circuitry
The Altera APEX architecture features up to four programmable phase-locked loops (PLLs) per device and contains ClockBoost, ClockShift, and ClockLock circuitry for increased performance and flexible clock-frequency multiplication and division. Together, these features provide significant improvements in system performance and bandwidth, enabling system-on-a-programmable-chip integration.
ClockBoost Circuitry
The ClockBoost circuitry enables the normal logic of the APEX device to operate at a faster or slower rate than the input clock frequency. It offers versatile frequency multiplication and division of m/(n * k) or m/(n * v), where m and k can be any integers from 1 to 256, n can be any integer between 1 to 16, and v can be any integer between 2 to 16. This advanced feature provides designers with true programmable clock synthesis, greatly enhancing design flexibility and system performance.
The ClockBoost feature creates variable-sized pulse widths by varying the multiplied frequency divided by the counter. It allows designers to implement time-domain multiplexed applications where a given circuit is used more than once per clock cycle. By using time-domain multiplexing, you can implement a given function with fewer logic cells or APEX embedded system blocks (ESBs), thereby improving device area efficiency by sharing resources within the device. See Figure 1.
Figure 1. ClockBoost Circuitry in APEX Devices
ClockShift Circuitry
APEX ClockShift circuitry provides programmable clock delay and phase shift. Programmable clock delay allows for incremental step delays of 0.4 ns to 1 ns, allowing the output clock to lead or lag the input clock by up to the particular clock period. The clock phase can be adjusted by 90º increments for phase shifting of 90º, 180º, and 270º; or any phase shift with a resolution of 360º/[5*(m/n)] relative to the input period (where 200 MHz < FIN *(m/n) < 400 MHz). This feature enables designers to have precise timing margins to meet high-speed interface requirements.
ClockLock Circuitry
The ClockLock circuitry uses a synchronizing PLL that reduces the clock delay and skew within a device. This reduction minimizes clock-to-output and setup times while maintaining zero hold times. You can also use the PLL output as an external clock resource to other devices on the printed circuit board (PCB). This feature, along with external feedback, enables designers to remove the clock skew among several devices on the board. The PLL can also dynamically adjust the output during operation to account for delay changes that occur because of temperature or voltage fluctuations, thus ensuring system stability.
APEX Offers Up to Four PLLs
APEX 20K devices have one PLL, which features the advanced ClockLock circuitry. The APEX PLL supports frequency multiplexing of 1x, 2x, and 4x. APEX 20KE and APEX 20KC devices feature an enhanced PLL feature set. The devices include up to four PLLs, which can be used independently. Two PLLs are designed for either general-purpose use or True-LVDS (low-voltage differential signaling) use (on devices that support LVDS I/O pins). The remaining two PLLs are designed for general-purpose use. EP20K200E and smaller devices have two PLLs; EP20K300E and larger devices have four PLLs. Table 1 outlines the APEX PLL features.
| Table 1. APEX PLL Features |
| Features |
APEX PLLs |
| Number of PLLs |
Up to 4 |
| Number of PLL outputs |
Up to 2 |
| Clock multiplication |
Any number up to 160 (1) |
| Clock division |
Any number up to 280 (1) |
| Coarse clock adjustment |
90º, 180º, 270º |
| Fine clock adjustment |
0.4 to 1 ns with 360º/[5*(m/n)] increments |
| Input frequency range |
1.5 to 420 MHz |
| Output frequency range |
1.5 to 420 MHz |
| 840-Mbps output for True-LVDS support |
Yes |
| T1/E1 frequency rate conversion |
Yes |
Note:
- Clock multlipication and division are calculated using m/(n*k). m and k are integers ranging from 1 to 256, and n is an integer from 1 to 16.
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