Advantages of APEX PLLs Over Virtex DLLs
The enhanced phase-locked loops (PLLs) found on both Altera APEX 20K and APEX 20KE devices play a key role in implementing system-on-a-programmable-chip designs. Altera has increased the number of PLLs to up to four, increasing device and board-level performance while minimizing clock skew and clock delay. Clock delay and clock skew can create problems on high-performance programmable logic devices (PLDs), affecting system timing and printed circuit board (PCB) reliability. To address these issues, designers can use either the PLLs found in APEX devices or the delay-locked loops (DLLs) found in Xilinx Virtex devices. Although both can be used to reduce the amount of skew within system clocks, PLLs are more flexible than DLLs for system frequency synthesis clocks.
APEX 20KE PLLs provide several advantages over Virtex-E DLLs, including:
- APEX 20KE PLLs support full multiplication and division capabilities.
- APEX 20KE ClockShift circuitry provides fine control of clock phase and clock delay.
- APEX 20KE PLLs support True-LVDS (low-voltage differential signaling) standard with data transfer rates up to 840 Megabits per second (Mbps).
- APEX 20KE PLLs support very low input clock frequencies (as low as 1.5 MHz).
- APEX 20KE PLLs filter out high-frequency jitter.
Table 1 compares the features of the APEX PLL and the Virtex DLL.
| Table 1. APEX 20KE PLL & Virtex-E DLL Comparison |
| Feature |
APEX 20KE PLL |
Virtex-E DLL (1) |
| Circuitry |
Analog |
Digital |
| Number of PLLs (DLLs) |
Up to 4 |
8 |
| Clock multiplication |
Any number up to 160 |
1x, 2x (2) |
| Clock division |
Any number up to 236 |
1.5, 2, 2.5, 3, 4, 5, 8, or 16 only |
| Coarse clock adjustment |
90º, 180º, 270º |
90º, 180º, 270º (3) |
| Fine clock adjustment |
0.4 to 1 ns resolution (up to 360º) |
None |
| Input frequency range |
1.5 to 420 MHz |
25 to 200 MHz |
| Output frequency range |
1.5 to 420 MHz |
1.5 to 320 MHz |
| 840-Mbps output for True- LVDS support |
Yes |
No |
| T1/E1 frequency rate conversion |
Yes |
No |
Notes for Table 1:
- Source: Virtex data sheet.
- Xilinx claims Virtex supports 4x clock multiplication by cascading two DLLs together.
- 90º and 270º are not usable for higher frequencies.
Conclusion
APEX PLLs, supported by the advanced APEX ClockLock, ClockBoost, and ClockShift circuitry, provide significant improvements in system performance and design versatility by minimizing clock skew and clock delay. The flexible clock synthesis and robust clock shift capabilities of APEX PLLs provide for precise phase and delay adjustment. Designers can increase system performance by minimizing tSU and tCO. PLLs allow support for high-performance I/O standards such as LVDS and provide the flexibility and the capability unattainable by Virtex-E DLLs. With these advantages, APEX PLLs dramatically increase system performance.
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