APEX II: Host Processor Interface
APEX™ II devices support processor interface protocols such as RapidIO™, HyperTransport™, and PCI-X.
| Table 1. APEX II Host Processor Support |
|
Interface Protocol
|
I/O Standards
|
Maximum Throughput
|
Maximum Number of Channels
|
Clock
|
| RapidIO |
LVDS |
32 Gbps (DDR) |
16 |
250 MHz to 1 GHz |
| HyperTransport |
HyperTransport
|
3.2 to 6.5 Gbps
|
2/4/8/16/32
|
200 to 800 MHz
|
| PCI-X |
LVTTL
|
4.2 Gbps
|
64
|
133-MHz
|
RapidIO
The RapidIO standard is an electronic data communications standard for interconnecting chips on a circuit board and circuit boards on a backplane. The high-performance, packet-switched RapidIO technology is used primarily in high-speed communications networking applications. APEX II devices feature support for LVDS, a RapidIO requirement. LVDS, combined with Altera's RapidIO intellectual property (IP) core, will provide an easy-to-implement, push-button RapidIO solution for APEX II designs.
HyperTransport
The HyperTransport I/O standard is an open standard bus designed to transfer data throughput up to 6.5 Gbps. APEX II devices feature dedicated HyperTransport I/O buffers with up to 1 Gbps per channel. APEX II devices feature embedded buffers that, along with Altera's IP offerings, provide a push-button, high-performance HyperTransport solution.
PCI-X
The peripheral component interconnect (PCI) local bus is a commonly-used general-purpose bus standard. PCI-X is a high-performance extension to the PCI local bus that is designed to meet the increasing I/O demands of technologies such as Fibre Channel, Gigabit Ethernet, and Ultra3 SCSI. APEX II devices are fully compliant with PCI-X standards up to 133 MHz.
|
Literature
> 
