APEX™ II devices support advanced memory-interfacing techniques to communicate with both static random access memory (SRAM) and dynamic random access memory (DRAM) devices at high speeds. APEX II I/O elements (shown in Figure 1) feature six registers, a latch, and a programmable delay element. The APEX II devices use zero-bus turnaround (ZBT), double-data rate (DDR), and quad-data rate (QDR) memory interfacing techniques to communicate with SRAM devices, and single-data rate (SDR) and DDR to communicate with DRAM devices, as shown in Table 1 and Figure 2.
| Table 1. APEX II External Memory Support | |||
|
Type |
Architecture |
I/O Standard |
Performance |
|---|---|---|---|
| SRAM |
ZBT SRAM |
LVTTL |
200 Mbps |
|
QDR SRAM |
HSTL |
668 Mbps | |
|
DDR SRAM |
HSTL |
334 Mbps | |
| DRAM |
SDR SDRAM |
LVTTL |
200 Mbps |
|
DDR SDRAM |
SSTL-2 Class II |
334 Mbps | |
Figure 1. APEX II I/O Element
Small to medium design memory requirements can be addressed entirely in the APEX II architecture with embedded system blocks (ESBs). For large memory requirements, designers can connect to external memory devices using any one of the supported memory interfaces. With 1.1 Mbits of internal memory and support for external RAM interfaces, APEX II devices are the ideal solution for both small and large memory applications.
Figure 2: APEX II Memory Interfacing Support
DDR
DDR interfacing accepts or outputs data on both the rising and falling edges of the clock. Addresses and control signals are registered at every positive clock edge, as shown in Figure 3. DDR doubles the memory bandwidth by transferring data twice per cycle. DDR SDRAM uses the SSTL-2 II I/O standard and can be clocked at 167 MHz for a maximum throughput of 334 Mbps per pin. DDR SRAM uses the HSTL I/O standard and can be clocked at 167 MHz for a maximum throughput of 334 Mbps per pin. APEX II I/O elements incorporate dedicated I/O circuitry for DDR SRAM/SDRAM interfacing.
Figure 3. Double Data Rate
ZBT
ZBT SRAM is synchronous, fast-static RAM designed to eliminate dead bus cycles during back-to-back read/write and back-to-back write/read cycles, providing 100% bus utilization as shown in Figure 4. ZBT SRAM eliminates data bus dead time by beginning a new access cycle on every clock edge, regardless of whether the next cycle is a consecutive read or write or a transition between a read and write, and eliminates the asymmetry between the read and write cycles. ZBT uses the LVTTL I/O standard, and APEX II devices can support ZBT up to 200 Mbps per pin using a 200-MHz clock.
Figure 4. Zero Bus Turnaround
QDR
QDR SRAM uses DDR technology on separate read and write ports, which results in four data throughputs per clock cycle as shown in Figure 5. The dedicated input and output ports free eliminate bus contention issues. Unilateral buses also simplify board design and facilitate high-frequency designs. QDR SRAM uses the HSTL I/O standard, and APEX II devices can support QDR at 668 Mbps using a 167 MHz clock.
Figure 5. Quad Data Rate
