The Altera® True-LVDS™ solution features embedded serialization/deserialization (SERDES) circuitry, enhanced phase-locked loops (PLLs), embedded differential I/O buffers, and dedicated clock-data synchronization (CDS) circuitry for a high-performance, low-power LVDS implementation capable of data transfers at up to 1 Gbps. APEX™ II devices address the high-performance requirements of the latest and emerging LVDS-based I/O interfaces such as UTOPIA Level 4, POS-PHY Level 4, LCS, HyperTransport, and RapidIO. In addition to high-speed LVDS support, APEX II devices are capable of serial transmission using other popular differential I/O standards including low-voltage positive emitter coupled logic (LVPECL), pseudo-current mode logic (PCML), and HyperTransport. Table 1 summarizes the differential I/O support in APEX II devices.
Differential I/O Support
| Table 1. APEX II Differential I/O Support | ||||
| I/O Standard |
Maximum Number of Receiver Channels
|
Maximum Number of Transmitter Channels
|
Maximum Data Throughput (Gbps)
|
|
|---|---|---|---|---|
| LVDS |
36
|
36
|
72
|
|
| LVPECL |
36
|
36
|
72
|
|
| PCML |
36
|
36
|
72
|
|
| HyperTransport |
36
|
36
|
72
|
|
Unparalleled LVDS Performance
APEX II devices support 1-Gbps LVDS on 36 input and 36 output channels in all device densities and differential standards. They also support two independent clock domains, resulting in 72-Gbps differential I/O bandwidth on the device.
| Table 2. High-Speed Interface Support | ||||
| Interface |
I/O Standard
|
Maximum Throughput
|
Channels
|
Clock
|
|---|---|---|---|---|
| Utopia L4 |
LVDS
|
10.0
|
32
|
415 MHz
|
| POS-PHY Level 4 |
LVDS
|
10.0
|
17
|
622 MHz
|
| LCS |
LVDS
|
10.0
|
72 or 84
|
200 MHz
|
| HyperTransport |
LVDS
|
3.2 - 6.5
|
2, 4, 8, 16, or 32
|
200 - 800 MHz
|
| RapidIO |
LVDS
|
32.0
|
16
|
250 MHz - 1 GHz
|
Clock-Data Synchronization
CDS circuitry synchronizes incoming data streams from multiple high-speed sources to a common system clock. Since synchronization is performed on a channel-by-channel basis, the distances between the receiving device and each of the transmitting devices can vary. The CDS-equipped APEX II devices can resolve varying skew between multiple channels, simplifying printed circuit board designs and eliminating the need for trace balancing through mitering. Figure 1 illustrates CDS in APEX II devices.
Figure 1. CDS in APEX II Devices
