Excalibur Devices Overview

Altera's Excalibur™ device family integrates a capable processor subsystem with the APEX™ FPGA architecture.

Note: While Altera continues to sell Excalibur devices, this product family is not recommended for new designs. Designs requiring embedded processors should consider Altera's Nios^® II processor.

Each Excalibur device integrates an ARM922T™ processor (a 32-bit RISC processor from ARM^® Inc. with associated caches and a memory management unit (MMU)), along with single and dual-port SRAM memory, memory controllers (SDRAM and expansion bus interface), peripherals, and debugging modules. Excalibur devices also support the AMBA™ high-performance bus architecture that allows full-speed system operation of the processor, dedicated bus bridges, and dual-port SRAM to provide interfaces to the logic portion of the device.

The integrated SDRAM controller supports either single data rate (SDR) or double data rate (DDR) SDRAM at up to 133 or 266 MHz, respectively, and supports up to 512 Mbytes of SDRAM. An expansion bus interface compatible with industry-standard flash memory, SRAM, and memory-mapped peripherals complements the SDRAM controller in Excalibur devices. The expansion bus interface can support up to four external devices, each up to 32 Mbytes. In addition to the memory controllers, the stripe also includes several other standard peripherals, including a UART, 32-bit general-purpose timer, interrupt controller, and watchdog timer.

Debugging functions are achieved through a Joint Action Test Group (JTAG) port, and an embedded trace (ETM9™) module assists in software debugging and real-time capture of events when used in conjunction with third-party trace modules.

The FPGA section is based on Altera's APEX 20KE device family, which contains up to one million typical gates of logic and, in the case of Excalibur devices, 4,160 to 38,400 logic elements (LEs). FPGAs with such densities provide access to a wide range of intellectual property (IP) cores, including Ethernet media access controllers (MACs), PCI interfaces, and finite impulse response (FIR) filters. These IP cores can integrate with the Excalibur design flow via SOPC Builder and are available from both Altera and third-party vendors. Providing dedicated interfaces between the processor and the FPGA optimizes the data flow between the two elements, and allows the FPGA to handle data path applications while the processor operates in the control plane.

For more information about Excalibur devices, visit the Excalibur device features page.

Excalibur devices are offered in three device configurations, as shown in Table 1.

Notes:

1. Pitch = 1.00 mm; area = 529 mm2.
2. Pitch = 1.00 mm; area = 729 mm2.
3. Pitch = 1.00 mm; area = 1,089 mm2.

Speed Grades

Excalibur devices come in three speed grades, as outlined in Table 2.

Note to Table 2:

1. All Excalibur devices have FPGA phase-locked loops (PLLs) available in addition to the stripe PLLs.

Related Links

• Nios Embedded Processor System Development
• Embedded Software Products
• ARM Ltd.