The microprocessor subsystem (or embedded stripe) in Excalibur devices includes the 32-bit ARM922T processor with AMBA advanced high-performance bus (AHB) bus structure, SRAM and dual-port SRAM memories, flash, SRAM, and SDRAM interfaces, and peripherals. The subsystem also contains Joint Test Action Group (JTAG) debugging facilities and an ETM9 embedded trace macrocell.
Figure 1 shows the microprocessor subsystem found in Excalibur devices.
Figure 1. Excalibur Device Block Diagram
- MMU = Memory management unit
- PLD = Programmable logic device
- EBI = Expansion bus interface
AHB Bus Structure
To maintain maximum system performance, the microprocessor subsystem's dual AMBA AHB structure allows optimum performance during accesses to slow peripherals. The AHB1 single master bus runs at the full processor speed, while AHB2 has multiple masters (including a master from the FPGA), and runs at one-half the speed of AHB1. For more details on the AMBA AHB bus structure, see the ARM922T architecture web page.
Excalibur devices implement multiple internal clock domains. The processor, dual-AHB bus structure, and SDRAM controller all have their own clock domains. Two dedicated programmable phase-locked loops (PLLs) control these clock domains: one PLL generates the clock for the AHB1 and AHB2, and the other PLL generates the clock for the SDRAM controller. The AHB1 processor bus and SDRAM bus run at speeds up to 200 MHz (with fAHB2 = fAHB1/2) and 133 MHz, respectively. The clock domains are independent and adhere to the APEX PLL specification and clock signals.
FPGA Configuration Logic
Excalibur devices may be configured several ways. The processor can boot independently from the FPGA, and it contains the configuration logic to program the FPGA from data stored either in external (flash) memory or downloaded into on-chip SRAM. Unlike FPGA solutions, Excalibur devices can be reconfigured at any time via processor control, while the processor continues to run. This can be done via a setup sequence, or via auto-detection when configuration is required.
In addition, the processor memory spaces can be reconfigured using traditional FPGA configuration modes and memory. In this event, the processor is held in reset, then allowed to boot only when the FPGA configuration is complete.
Microprocessor Subsystem to FPGA Interfaces
The value of integrating a processor and FPGA increases substantially with the incorporation of multiple high-speed data exchange interfaces. The Excalibur processor has two AHB bridges on AHB2 that allow the processor (or other master within the subsystem) and the FPGA to each act as bus masters on the AHB2 bus. By functioning as bus master, the master can initiate a data transfer through the bus bridge in either direction. Moreover, allowing the FPGA and the processor to initiate bus transfers enables the creation of complex systems that provide real-time interaction, between the processor and FPGA, to form complete system-on-a-programmable-chip (SOPC) designs.
The dual-port SRAM memory is accessible from both the FPGA and the processor. Data can be written to and read from this memory space, providing a simple shared data area for applications interfaces. One such application is for the processor to interface to a digital signal processing (DSP) function implemented in the FPGA by reading and writing the appropriate memory spaces within the dual-port memory.