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Arria GX FPGA Overview

Overview Applications Design Resources Literature Getting Started

ArriaTM GX FPGAs are an award-winning, midrange FPGA family. Arria GX FPGAs share the same transceiver technology as the proven Stratix® II GX family. By streamlining the transceivers and creating efficient I/O cells, Arria GX FPGAs provide a cost-effective solution to connect with today's mainstream high-speed protocols.  Table 1 outlines the protocols supported by Arria GX FPGAs.

Table 1. Protocols Supported by Arria GX FPGAs
Standard Data Rate (Gbps)
3G Basic 3.125
SD, HD, 3G SDI 0.27, 1.488, 2.97
PCI Express 1.1 (x1, x4) 2.5
Serial RapidIO® (1x, 4x) 1.25, 2.5

Serial RapidIO (1x)

3.125
Common Public Radio Interface (CPRI) 2.5, 3.072
Open Base Station Architecture Initiative (OBSAI) 0.768, 1.536, 3.072

Gigabit Ethernet

1.25
XAUI 3.125
SerialLite II Up to 3.125
SGMII 1.25

Tables 2 and 3 list the Arria GX family devices and packaging information, respectively. All device densities that are available in the same package are vertically migratable (that is, they share the same VCC, GND, in-system programmables, and dedicated input pins).

Table 2. Arria GX Device Family
Device EP1AGX20 EP1AGX35 EP1AGX50 EP1AGX60 EP1AGX90
Transceiver Channels 4 4 8 4 8 4 8 12 12
Equivalent LEs (1) 21,580 33,520 50,160 60,100 90,220
Total
Memory Bits

1,229,148

1,348,416 2,475,072 2,528,640 4,477,824
18 x 18
Multipliers
40 56 104 128 176
PLLs (2) 4 4 4 4, 8 4 8 8
Availability (3)

Notes:

  1. LE = Logic Element
  2. PLL = phase-locked loops
  3. All packages except F484. F484 packages will be available in September.
Table 3. Arria GX Packaging

Device

EP1AGX20

EP1AGX35

EP1AGX50

EP1AGX60

EP1AGX90

Transceiver

Channels

4

4

8

4

8

4

8

12

12

F484

User I/O Pins

230

230

-

229

-

229

-

-

-

F780

User I/O Pins

341

-

341

-

350

-

350

-

-

F1152

User I/O Pins

-

-

-

-

514

-

-

514

538

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