Arria GX FPGA Transceiver Overview
The embedded transceivers in ArriaTM GX FPGAs are built from the same robust transceivers found in Stratix® II GX FPGAs. Arria GX transceivers deliver best-in-class signal integrity and low power consistent with the robust transceiver building blocks found in Stratix II GX FPGAs. Arria GX transceivers are optimized for mainstream serial I/O applications and support serial I/O protocols ranging from 600 Mbps to 3.125 Gbps. Serial protocols supported by Arria GX transceivers include:
Table 1 highlights the features and benefits of Arria GX FPGAs.
| Table 1. Arria GX Transceiver Features Summary |
| Feature |
Description |
| Excellent Signal Integrity |
Arria GX transceivers are based on proven Altera® transceiver technology developed for Stratix II GX FPGAs to ensure standards compliance for the supported protocols. |
| Low Power |
The transceivers dissipate only 125 mW per channel at 2.5 Gbps. |
| Channel Equalization |
The transceivers can equalize a serial channel with fixed equalization settings for transmit pre-emphasis and receive equalizations. |
PCS Support
(Hard IP) |
The transceivers include the following PCS layer: PCI Express PIPE-Compliant PCS, Gigabit Ethernet state machine, and SRIO. |
| System-Level Diagnostics |
The transceivers support serial loopback, reverse serial loopback, and pseudo-random binary sequence (PRBS) generator and checker. |
Additional Transceiver Features
- High-speed serial support up to 3.125 Gbps
- Devices available with up to 12 high-speed serial transceiver channels
- One transceiver quad can drive two serial protocols
- Individual transmitter and receiver channel power-down capability for reduced power consumption during non-operation
- Selectable on-chip termination resistors for improved signal integrity on a variety of transmission media
- Receiver indicator for loss of signal
- Built-in self test (BIST)
- Hot insertion/removal protection circuitry
- 8B/10B encoder/decoder performs 8-bit to 10-bit encoding and 10-bit to 8-bit decoding
- Phase compensation FIFO buffer performs clock domain translation between the transceiver block and the logic array
- Receiver FIFO buffer resynchronizes the received data with the local reference clock
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