FPGA, CPLD, and ASIC solutions from Altera
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Altera Devices Overview

Home > Products > Devices > Altera Devices Overview
High-End FPGAs Description/Unique Features
Stratix IV logo
  • Fourth-generation Stratix® FPGA family
  • Highest performance, highest density, and lowest power 40-nm FPGAs
  • Best-in-class 11.3-Gbps transceivers and high-performance memory interfaces deliver unprecedented system bandwidth with superior signal integrity
Stratix III Logo
  • Third-generation Stratix FPGA family, the industry’s lowest power, high-performance 65-nm FPGAs, recommended for designs starting now
  • Logic rich (L), enhanced for digital signal processing (DSP) and memory (E), and transceiver (GX) variants
  • Targets high-end core system processing designs, supported by industry leading FPGA design tools, and provides a risk-free path to HardCopy® ASICs
Stratix II Logo
  • Second-generation high-performance 90-nm FPGA family, recommended for production projects now
  • Includes best-in-class 6.375-Gbps transceiver (GX) variant available today.
  • Advanced FPGA architecture, high-performance adaptive logic module (ALM) with 8-input fracturable look-up table (LUT), large on-chip memory, embedded DSP blocks, high-speed external interface support, and risk-free path to HardCopy ASICs
Stratix Logo
  • First-generation Stratix FPGA family. Stratix II and Stratix III families now provide higher performance at lower cost
  • Mid-performance, embedded DSP blocks, on-chip memory, flexible I/O
  • Broad range of IP support including Nios® II processors

Midrange FPGAs

Arria II logo
  • Cost-optimized 40-nm FPGAs with transceivers
  • Offers lowest total power for transceiver-based applications
  • Up to 16 transceivers at 3.75 Gbps, rich in DSP and RAM, with more performance than other devices in its class
Arria GX Logo
  • Arria GX 90-nm FPGAs with transceivers
  • Optimized for 3-Gbps serial I/O applications
  • Simple solution for bridging and end-point applications

Low-Cost FPGAs

Cyclone IV Logo
  • Fourth generation in the Cyclone® series of lowest cost, lowest power FPGAs
  • Two variants: Cyclone IV GX FPGAs with integrated 3.125-Gbps transceivers and Cyclone IV E FPGAs
  • Broad range of intellectual property (IP) support including Nios II embedded processor support
Cyclone III Logo
  • Third generation in the Cyclone series of lowest cost FPGAs
  • Unprecedented combination of power, functionality, and cost
  • Broad range of IP support including Nios II embedded processor support
Cyclone II Logo
  • Second generation in the lowest cost FPGA series
  • Embedded 18 x 18 DSP multipliers, on-chip memory, and midrange speed I/O
  • Broad range of IP support, including Nios II embedded processor support
Cyclone Logo
  • First generation in the lowest cost FPGA series, where cost is paramount
  • On-chip memory, lower density applications, low to moderate speed I/O
  • Broad range of IP support including Nios II embedded processor support

Low-Cost CPLDs

MAX II Logo
  • Instant-on, non-volatile, single-chip CPLD solution
  • Lowest cost, lowest power (1/10th of MAX® CPLD), highest density CPLD
  • On-board user flash memory. 1.8-V, 2.5-V, and 3.3-V supply voltages
MAX Logo
  • Instant-on, non-volatile, low-cost CPLD for low density solutions
  • Deterministic timing
  • 5.0-V I/O support. 2.5-V, 3.3-V, and 5.0-V supply voltages

HardCopy ASICs

HardCopy IV logo
  • Fifth-generation in the HardCopy® ASIC series
  • Benefits of FPGA and benefits of ASIC deliver fast time-to-market and fast time-to-profit
  • HardCopy IV GX devices with 6.5-Gbps transceivers and high-performance memory interfaces deliver excellent system bandwidth with superior signal integrity
HarCopy III logo
  • Benefits of FPGA and benefits of ASIC deliver fast time-to-market and fast time-to-profit
  • Low risk, low total cost ASIC for high-volume production
  • Low-risk prototyping using Stratix III FPGAs for true software/hardware co-design and fast system readiness
HardCopy II Logo
  • Low-cost HardCopy ASIC for high-volume production
  • Migrate Stratix II FPGA prototype to functionally equivalent, pin-compatible device
  • Increase core performance and reduce power by 50–70 percent compared to Stratix II FPGA prototype
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  • Product Selector
    • Compare Devices (Beta)
  • High-End FPGAs
    • About Stratix Series
    • Stratix IV (E, GX, GT)
      • Overview
        • Architecture
        • Density
        • Performance
        • Power
      • Transceivers (GX and GT)
      • End Markets & Applications
      • Design Resources
      • Literature
      • Getting Started
    • Stratix III (L and E)
      • Overview
      • End Markets & Applications
      • Design Resources
      • Literature
      • Getting Started
    • Stratix II (and GX)
      • Stratix II
        • Overview
        • Design Utilities
        • Features
        • Literature
      • Stratix II GX
        • Overview
        • Design Utilities
        • Features
        • Literature
    • Stratix (and GX)
      • Stratix
        • Overview
        • Design Utilities
        • Features
        • Literature
      • Stratix GX
        • Overview
        • Design Utilities
        • Features
        • Literature
  • Midrange FPGAs
    • About Arria Series
    • Arria II GX
      • Overview
        • Architecture
        • Power
      • Transceivers
      • End Markets & Applications
      • Design Resources
      • Literature
      • Getting Started
    • Arria GX
      • Overview
        • Architecture
        • Software
      • Transceivers
      • Applications
      • Design Resources
      • Literature
      • Getting Started
  • Low-Cost FPGAs
    • About Cyclone Series
    • Cyclone IV (E and GX)
      • Overview
        • Architecture
        • Power
      • Transceivers
      • End Markets & Applications
      • Design Resources
      • Literature
      • Getting Started
    • Cyclone III (and LS)
      • Overview
        • Architecture
        • Power
        • Security
      • End Markets & Applications
      • Design Resources
      • Literature
      • Getting Started
    • Cyclone II
      • Overview
      • Design Utilities
      • Features
      • Literature
    • Cyclone
      • Overview
      • Design Utilities
      • Features
      • Literature
  • CPLDs
    • About MAX Series
    • MAX II (and G, Z)
      • Overview
        • Architecture
        • Power
        • Unique Features
      • Applications
      • Design Resources
      • Literature
      • Getting Started
    • MAX 3000A
      • Overview
      • Design Utilities
      • Features
      • Literature
  • ASICs
    • About HardCopy Series
    • HardCopy IV (E and GX)
      • Overview
        • Power
        • SEU
        • Performance
      • Transceivers
      • End Markets & Applications
      • Literature
      • Getting Started
    • HardCopy III
      • Overview
        • Architecture
        • Power
        • SEU
        • Performance
      • End Markets & Applications
      • Literature
      • Getting Started
    • HardCopy II
      • Overview
        • Power
        • SEU
        • Performance
      • End Markets & Applications
      • Literature
      • Getting Started
  • Device-Specific Offerings
    • RoHS Compliant
      • Packaging Literature
    • Extended Temperature
    • Enhanced Temperature
    • Military Temperature
  • Configuration Devices
    • Enhanced Configuration
      • Overview
      • Design Utilities
      • Features
      • Literature
    • Serial Configuration
      • Overview
      • Design Utilities
      • Features
      • Literature
  • Mature Products
    • Product Listing
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