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   Stratix II GX
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   Arria GX
  
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Altera Devices Overview

    Low-Cost FPGAs

       Description/Unique Features
Cyclone III Logo
  • Third-generation in the Cyclone® lowest cost FPGA series.
  • Unprecedented combination of power, functionality, and cost.
  • Broad range of intellectual property (IP) support including Nios® II embedded processor support.
Cyclone II Logo
  • Second-generation in the lowest cost FPGA series.
  • Embedded 18 x 18 digital signal processing multipliers, on-chip memory, and mid-range speed I/O.
  • Broad range of IP support including Nios II embedded processor support.
Cyclone Logo
  • First-generation in the lowest cost FPGA series, where cost is paramount.
  • On-chip memory, lower density applications, low to moderate speed I/O.
  • Broad range of IP support including Nios II embedded processor support.

    High-End FPGAs

Stratix III Logo
  • Third-generation Stratix® FPGA family, the industry’s lowest power high-performance FPGAs, recommended for designs starting now.
  • Logic rich (L), enhanced for memory and DSP (E), and transceiver-based (GX) variants.
  • Targets high-end core system processing designs, supported by industry leading FPGA design tools. Risk-free path to HardCopy® structured ASIC.
Stratix II Logo
  • Second-generation high-performance FPGA family, recommended for production projects now.
  • Includes best-in-class 6.375-Gbps GX transceiver variant available today.
  • Advanced FPGA architecture, high-performance adaptive logic module (ALM) with 8-input fracturable look-up table (LUT), large on-chip memory, embedded DSP blocks, and high-speed external interface support. Risk-free path to HardCopy structured ASIC.
Stratix Logo
  • First-generation Stratix FPGA family. Stratix II and Stratix III families now provide higher performance at lower cost.
  • Mid-performance, embedded digital signal processing (DSP) blocks, on-chip memory, flexible I/O.
  • Broad range of IP support including Nios II processors.

    Low-Cost Transceiver FPGAs

Arria GX Logo


  • Low-cost, risk-free FPGAs with transceivers.
  • Optimized for PCIe, GbE, and SRIO.
  • Simple solution for bridging and end-point applications.

    Structured ASICs

HarCopy III logo
  • Fourth-generation in the HardCopy® structured ASIC series.
  • Low risk, low total cost ASIC for high-volume production.
  • Seamless prototyping using Stratix III FPGAs for true software/hardware co-design and fast system readiness.
HardCopy II Logo
  • Low-cost structured ASIC for high-volume production.
  • Migrate Stratix II prototype to functionally equivalent, pin-compatible device.
  • Increase core performance and reduce power by 50-70 percent compared to Stratix II FPGA prototype.
HardCopy Logo
  • Seamless migration from Stratix FPGA as prototype to structured ASIC.
  • Low-cost structured ASIC for high-volume production.
  • Supported by all major EDA vendors, 40 percent lower power than Stratix FPGAs, and a 50 percent performance increase.

    Low-Cost CPLDs

 
MAX II Logo
  • Instant-on, non-volatile, single-chip CPLD solution.
  • Lowest cost, lowest power (1/10th of MAX®), highest density CPLD.
  • On-board user flash memory. 1.8-V, 2.5-V, and 3.3-V supply voltages.
MAX Logo
  • Instant-on, non-volatile, low-cost CPLD for low density solutions.
  • Deterministic timing.
  • 5.0-V I/O support. 2.5-V, 3.3-V, and 5.0-V supply voltages.

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