Configuration Devices Advanced Features
Altera's single-chip configuration solution—enhanced configuration devices—offers advanced features such as a decompression engine, dynamic configuration, 8-bit parallel configuration, external flash interface, in-system programmability (ISP), and a programmable clock, all of which are described below.
Data Compression/Decompression Engine
Altera’s largest enhanced configuration device, the EPC16 device, features 30 Mbits of configuration memory, which is possible because of the device's 16-Mbit flash chip and incorporated data compression/decompression scheme that effectively doubles the configuration memory.
The Quartus® II software generates and efficiently compresses configuration data by 1.8x. The configuration device then downloads the data, which is then interpreted by its decompression engine and sent to the programmable logic device (PLD), as shown in Figure 1. With compression/decompression, a single EPC16 device can configure the Stratix® II EP2S60 device or the Stratix EP1S80 device.
Figure 1. Data Compression/Decompression Process
Dynamic Configuration
The high pace of change and innovation in today's high-tech market drives the demand for quick in-system design updates with minimal system downtime. The page mode feature in Altera's enhanced configuration devices meets these demands because it allows the devices to store up to eight dynamically sized pages.
The page mode feature allows designers to store multiple configurations for their PLDs in a single configuration device and dynamically switch the functionality of the PLD by simply asserting page mode pins, as shown in Figure 2.
Figure 2. Page Mode Feature
For example, Page 0 could contain a configuration that enables the PLD to only process data packets while Page 1 could contain another configuration that will enable the same PLD to process both data and voice packets. Depending on the end user's choice, the user can quickly configure one system for either functionality with minimal downtime.
This feature, when combined with Stratix II, Stratix II GX, Stratix, or Stratix GX devices, is ideal for remote-system upgrades. These eight dynamically-sized pages can also store configuration files for multiple PLDs on the board—eliminating the need for multiple configuration devices. Having a single device saves valuable board space and significantly reduces board complexity.
8-Bit Parallel Configuration
The enhanced configuration devices give designers many options for programming PLDs. These methods include:
- Traditional serial mode
- Multiple configuration mode where up to eight PLDs can be programmed in parallel
- New, fast, 8-bit parallel mode
With devices that support 8-bit parallel programming (such as Stratix II, Stratix II GX, Stratix, Stratix GX, and APEX™ II devices) enhanced configuration devices can download the programming data in an 8-bit parallel stream--reducing the configuration time by a factor of eight. Combined with faster clock speeds enabled by the programmable clock, these configuration devices offer dramatically reduced configuration times, as shown in Figure 3. Enhanced configuration devices can also program multiple PLDs in a chain, either in the traditional serial mode or with the 8-bit parallel programming mode.
Figure 3. Reduced Configuration Times with 8-Bit Parallel Configuration
External Flash Interface
Altera’s enhanced configuration devices provide an abundance of memory. Unlike older configuration devices where memory can only be used for configuration, enhanced configuration devices have flash memory that can be implemented as general-purpose memory. Microprocessors and PLDs can both use general-purpose memory, making enhanced configuration devices a combination flash/configuration solution and further reducing board space requirements.
Designers can access the flash memory through an industry-standard external flash interface, as shown in Figure 4. The combination of this flash interface with the flash memory’s dedicated boot block enables an enhanced configuration device to boot-up an external processor, such as the Nios® II soft core embedded processor, after configuring the PLD.
Figure 4. External Flash Interface
In-System Programmability
In-system programmability (ISP) support is provided through the industry-standard Joint Test Action Group (JTAG) interface and is compliant with IEEE Std. 1532. All enhanced configuration devices are ISP-capable, increasing design flexibility by allowing design updates in-system, and reducing costs by streamlining the manufacturing process.
Programmable Clock
The programmable clock feature in the enhanced configuration devices provides designers with multiple clock speeds for increased design flexibility and faster configuration times. The user can choose from an internally generated 10-MHz, 33-MHz, 50-MHz, or 66-MHz clock, or from an external clock of up to 133 MHz, as shown in Figure 5. Using the Quartus II software, designers can modify the clock by adjusting the N factor in the clock divider unit to any required frequency. This process is typically as simple as setting the desired frequency in the software.
Figure 5. Programmable Clock Feature
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