| Table 1. Enhanced Configuration Device Features |
|
Feature |
Benefit |
| High Density |
A single EPC16 configuration device, with compression technology, provides up to 30 Mbits of configuration memory. |
| Reduced Configuration Times |
The combination of true parallel programming (8 to 1) and higher clock speeds (up to 66 MHz) enabled by the programmable clock dramatically reduces configuration times and allows for quick in-system updates. |
| Dynamic Configuration |
The page mode feature allows dynamic programmable logic device (PLD) updates by storing multiple configuration files in up to eight dynamically sized pages in a single configuration device. This feature is useful for field upgrades as well as development. |
| External Flash Interface |
An external flash interface allows designers to use any of the memory not consumed for configuration as general-purpose memory. |
| 8-bit Parallel Programming |
8-bit parallel programming enables the device to configure a PLD up to 8 times faster. A single configuration device can also configure up to eight devices in parallel. |
| Selectable Clock |
Designers can choose to use a 10-MHz, 33-MHz, 50-MHz, or 66-MHz clock generated by the internal oscillator, or an external clock of up to 133 MHz. The selectable clock feature provides flexibility in board design while enabling faster configuration times. |
| In-System Programmability |
ISP in Altera's configuration devices is supported through Jam™ STAPL and is compliant with IEEE Std. 1532. ISP increases design flexibility by allowing design updates in-system and reduces costs by streamlining the manufacturing process. |
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