Interface Bridging
With the increasing number of bus protocols supported by ASSP and microcontroller vendors, translation between interfaces is a growing problem that requires an inexpensive and easy solution. The MAX® II family of CPLDs is designed to support interface bridging applications, including voltage-level shifting (for example, 3.3 V in to 1.8 V out) bus translation applications (translating a proprietary language to an industry-standard language), multipoint bus bridging, serial-to-parallel and parallel-to-serial bus conversions, and encryption (where MAX II CPLDs encrypt and/or decrypt data).
Table 1 highlights MAX II CPLD features that support interface bridging applications.
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Table 1. MAX II CPLD Application Solutions: Interface Bridging
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MAX II CPLD Features
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Benefits
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| Lowest Cost per I/O Pin |
Current bus-width requirements make higher I/O counts a necessity. MAX II CPLDs offer the lowest cost per I/O pin solution in the market.
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PCI Compliance
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MAX II CPLDs are fully compliant with 3.3-V PCI at 66 MHz, allowing direct connections to the PCI bus—one of the most common bus systems in the industry.
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Flexible I/O Banks
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Multiple I/O banks support multiple I/O voltages. Programmable drive strength, Schmitt triggers, and an output enable (OE) per pin are all available on MAX II CPLDs to satisfy a broad range of I/O requirements.
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Second-Time Fitting
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The pin location on MAX II CPLDs can be altered based on the bus layout requirements. MAX II CPLDs enable high performance and flexible routing, even with locked pin assignments.
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Re-Programmability
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CPLDs offer the only complete solution to many of the system-specific problems related to bus bridging that require custom interfacing.
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Figure 1 shows how you can use MAX II CPLDs to implement a PCI bridge. The boards may be physically separated via a cable or as part of a backplane configuration. MAX II CPLDs can also act as repeaters for other bus systems, increasing the drive strength of the bus, and subsequently, the number of devices that can be supported on the bridge.
In this application, MAX II CPLDs enable the addition of an optional add-on board to the host PCI bus system. The two largest MAX II CPLDs are PCI-compliant and may be added to a 3.3-V PCI bus as a 32-bit PCI target at 66 MHz. The high-density MAX II CPLDs enable more complex bus applications to be supported (e.g., PCI target functions) at very low cost.
Figure 1. PCI Bus Bridge Using MAX II CPLDs
Figure 2 depicts how MAX II CPLDs can function as a crosspoint switch, which is used in many applications for enabling multi-point connections. Using programmable logic in this application enables the greatest flexibility to match the requirements of any specific design. In this application, the logic in the MAX II CPLD is divided into three major blocks:
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The switch matrix, for connecting any input to any output
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The configuration register, for reconfiguring connections during operation
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The address decoder, for decoding the output addresses of the configuration
Interface bridging requires a large number of I/O pins to support the bus interfacing, but not a lot of logic. Because MAX II CPLDs have the lowest cost per I/O pin, they provide the greatest cost optimization for this application.
Figure 2. Multipoint Connections Using a MAX II Low-Cost CPLD
Altera offers a number of tested and documented design examples that provide an easy starting point for implementing interface bridging functions. For more information, see MAX II and MAX Design Examples.
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Literature
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