CPLDs are commonly used to manage the configuration or initialization of a volatile device. Typical examples of components that require configuration or initialization include FPGAs, digital signal processors, ASSPs, and ASICs. Today’s increasingly complex devices, such as smart phone cellular handset designs, require a robust system configuration and initialization application solution. Table 1 highlights MAX® II CPLD features that meet these needs.
| Table 1. MAX II CPLD Application Solutions: System Configuration and Initialization | |
| Features | Benefits |
|---|---|
| Non-Volatile and Instant-On Capability | Configuration and initialization of the power-up sequence ensures that the configuration data is loaded before the devices become operational. |
| Real-Time ISP | Real-time ISP allows MAX II CPLDs to operate while downloading and storing a second programming bitstream, reducing system downtime. The re-programming occurs immediately or at the next power-up scheduled by the user. |
| Parallel Flash Loader Megafunction | The Parallel Flash Loader megafunction allows discrete non-JTAG-compliant flash memory devices to be configured via the MAX II JTAG port while connected to the automatic test equipment or in the field. This application reduces programming time of the discrete flash devices. |
| User Flash Memory | The MAX II device’s on-chip user flash memory stores up to 8 Kbits of data, eliminating the need for smaller external flash memory devices. |
| Re-Programmability |
With today’s multiple and ever-changing memory interface standards, the MAX II device’s flexible re-programmability enables interfacing to the discrete memory device with the lowest cost or greatest availability. |
| Industry's Lowest Power CPLDs |
Using low-power CPLDs to power-up other system devices only when needed reduces overall system power consumption and can also lower manufacturing and operating costs associated with power supply and heat dissipation. |
MAX II CPLDs enable a one-chip solution for programming the discrete flash memory and device configuration using the Parallel Flash Loader megafunction and application note (AN 386: Using the MAX II Parallel Flash Loader with the Quartus II Software (PDF)). As shown in Figure 1, the initial step of the configuration application demonstrates the flash controller application. This function configures the flash device using JTAG via the MAX II device JTAG pins.
The second step of the configuration application uses discrete flash to configure multiple FPGAs. This is a cost-effective, flexible solution utilizing any shared, low-cost flash memory device on a system board. Given the high densities available in the MAX II CPLD family, extremely complex configuration systems can be implemented, including having multiple pages within the flash to program the FPGA as needed.
Figure 1. FPGA Configuration Management and Flash Controller Using a MAX II CPLD
MAX II CPLDs reduce cost and board space by combining a two-chip solution into one. As shown in Figure 2, the FIFO configuration example demonstrates how configuration data for the FIFO buffers is stored in the user flash memory rather than in an external flash memory. The stored data can include information on the number of FIFO buffers, the number of data streams, and the almost empty/almost full offsets.
Figure 2. FIFO Configuration Management Using a MAX II CPLD
