I/O Expansion
To cost-effectively expand the general I/O capability of standard products, a high number of low-cost I/O pins becomes a key requirement for many system-level designs. The low-cost, flexible I/O capability of MAX® II CPLDs is an ideal complement to today’s I/O pin-constrained ASSPs and microcontrollers. Table 1 describes some of the MAX II CPLD features that ease I/O expansion design challenges.
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Table 1. MAX II CPLD Application Solutions: I/O Expansion
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Features
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Benefits
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Lowest Cost per I/O Pin
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The MAX II device’s cost per I/O pin is the lowest in the market.
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Routing Flexibility
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The logic element-based MAX II architecture enables more flexible routing compared to traditional macrocell-based CPLDs, even with locked pin assignments.
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Flexible I/O Banks
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Multiple I/O banks support multiple I/O voltages. Programmable drive strength, Schmitt triggers, and an output enable (OE) per pin are all available on MAX II CPLDs to satisfy a broad range of I/O requirements.
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Re-Programmability
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Provides flexibility to solve system-specific problems and supports last minute changes.
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Figure 1 shows how a microcontroller with limited I/O capability can control many devices in a system by using only a two-wire serial bus. In this application example, the MAX II CPLD interfaces to the serial bus input and then distributes instructions to control multiple devices (in this case, the fan motor controllers). The MAX II CPLD‘s on-board user flash memory can store information, such as the frequency or the duty cycle of the motors.
Data can also be converted from parallel to serial, such as taking information from the analog-to-digital converters (ADC) in parallel and communicating it to the microcontroller via the two-wire serial bus.
Figure 1. Expanding a Serial Bus Using MAX II CPLDs
Note:
- UFM: user flash memory
Many microprocessors are limited in I/O capability but need to distribute control signals to multiple devices around the system. Figure 2 shows how MAX II CPLDs can control a large number of devices on the board with only a minimal number of inputs from the host processor, thereby reducing I/O overhead support on the processor.
MAX II CPLDs, with the lowest cost per I/O pin, provide the best cost optimization for these I/O-intensive applications.
Altera provides design examples for accomplishing IO expansion in MAX II CPLDs. See MAX II and MAX Design Examples for more information.
Figure 2. Control Signal Distribution Using MAX II CPLDs
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Literature
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