FPGA, CPLD, and ASIC solutions from Altera
  • Download Center
  • Literature
Sign in/register
myAltera Account
Welcome
  •   myAltera
  •   Logout
  • Products
    • Devices
    • Design Software
    • Intellectual Property
    • Development Kits/Cables
    • Design & Support Services
    • Literature
  • End Markets
    • Automotive
    • Broadcast
    • Computer & Storage
    • Consumer
    • Industrial
    • Medical
    • Military
    • Test & Measurement
    • Wireless
    • Wireline
  • Technology
    • DSP
    • External Memory
    • Embedded Processing
    • Transceivers
    • Parallel I/O
    • Signal Integrity
    • System Integration
  • Training
    • Training Courses
    • University Program
    • Webcasts & Videos
    • Demonstrations
    • Events Calendar
  • Support
    • Design & Support Resources
    • Knowledge Database
    • Devices
    • Design Software
    • Intellectual Property
    • Development Kits/Cables
    • Design Examples
    • Downloads
    • User Communities/Forums
    • mySupport
  • About Altera
    • About Us
    • Environmental
    • Customer Successes
    • Partners
    • Newsroom
    • Investor Relations
    • Jobs
    • Contact Us
  • Buy Online
    • Devices
    • Design Software
    • Development & Education Kits
    • Cables & Programming Hardware
    • Intellectual Property
  • Entire Site
  • Part Number
  • Knowledge Database
  • Support & Technical Docs
  • Forums & Wiki
Username:  
Password:  
 
Forgot my username or password
Don't have myAltera account? Register Now.
Enter your email address:

I/O Capabilities in MAX II CPLDs

Home > Products > Devices > MAX II (and G, Z) > Overview > Architecture > I/O Capabilities in MAX II CPLDs

Altera® MAX® II CPLDs offer I/O capabilities that optimize ease-of-use and system integration. Table 1 lists the I/O standards supported in MAX II CPLDs. Table 2 lists MAX II I/O features and benefits.

Table 1. MAX II CPLD I/O Standards

I/O Standard

Performance

3.3-V LVTTL/LVCMOS

300 MHz

2.5-V LVTTL/LVCMOS

220 MHz

1.8-V LVTTL/LVCMOS

200 MHz

1.5-V LVCMOS

150 MHz

3.3-V PCI (1)

66 MHz

Table 2. MAX II CPLD I/O Features and Benefits

Feature

Benefit

3.3-, 2.5-, 1.8- & 1.5-V LVTTL/LVCMOS

Enables broad application support and compatibility with other devices on board

MultiVolt™ I/O With Multiple I/O Banks

Up to four I/O banks seamlessly interface to other devices at 3.3-, 2.5-, 1.8-, and 1.5-V voltage levels

PCI Support (1)

Enables support for the 32-bit, 66-MHz PCI standard

Schmitt Triggers

Aids in noise tolerance on inputs with up to 300 mV of hysteresis on 3.3-V inputs and 160 mV of hysteresis on 2.5-V inputs

Programmable Drive Strength and Slew Rate

Allows you to control and improve signal integrity

Single Output Enable (OE) per I/O Pin

Numerous OEs allow you to use smaller devices, reducing cost

Hot-Socketing Support

Enables safe insertion or removal of device from powered systems

Fast I/O Connection

Enables fast tPD and tCO timing

Note:

  1. PCI support is available on EPM1270 and EPM2210 devices.

Fast I/O Connection

The MAX II CPLD I/O element (IOE) includes a dedicated connection path from an adjacent logic element (LE) associated with the I/O pin that results in fast tPD and tCO performance parameters. Quartus® II software automatically selects the dedicated path to speed-up I/O performance. Figure 1 illustrates the IOE in MAX II CPLDs.

Figure 1. MAX II CPLD I/O Element

Figure 1. MAX II I/O Element

MAX II CPLD I/O Banks

There are two I/O banks in the EPM240 and EPM570 devices and four I/O banks in the EPM1270 and EPM2210 devices. Each I/O bank has its own VCCIO pin and can be configured independently to support 1.5-, 1.8-, 2.5-, and 3.3-V interfaces. Each I/O bank can support an independent I/O standard. Figure 2 shows the I/O bank configuration in MAX II CPLDs.

Figure 2. MAX II CPLD I/O Bank Configuration

Related Links

  • Using MAX II Devices in Multi-Voltage Systems (PDF) chapter of the MAX II Device Handbook
Rate This Page


  • Product Selector
    • Compare Devices (Beta)
  • High-End FPGAs
    • About Stratix Series
    • Stratix IV (E, GX, GT)
      • Overview
        • Architecture
        • Density
        • Performance
        • Power
      • Transceivers (GX and GT)
      • End Markets & Applications
      • Design Resources
      • Literature
      • Getting Started
    • Stratix III (L and E)
      • Overview
      • End Markets & Applications
      • Design Resources
      • Literature
      • Getting Started
    • Stratix II (and GX)
      • Stratix II
        • Overview
        • Design Utilities
        • Features
        • Literature
      • Stratix II GX
        • Overview
        • Design Utilities
        • Features
        • Literature
    • Stratix (and GX)
      • Stratix
        • Overview
        • Design Utilities
        • Features
        • Literature
      • Stratix GX
        • Overview
        • Design Utilities
        • Features
        • Literature
  • Midrange FPGAs
    • About Arria Series
    • Arria II GX
      • Overview
        • Architecture
        • Power
      • Transceivers
      • End Markets & Applications
      • Design Resources
      • Literature
      • Getting Started
    • Arria GX
      • Overview
        • Architecture
        • Software
      • Transceivers
      • Applications
      • Design Resources
      • Literature
      • Getting Started
  • Low-Cost FPGAs
    • About Cyclone Series
    • Cyclone IV (E and GX)
      • Overview
        • Architecture
        • Power
      • Transceivers
      • End Markets & Applications
      • Design Resources
      • Literature
      • Getting Started
    • Cyclone III (and LS)
      • Overview
        • Architecture
        • Power
        • Security
      • End Markets & Applications
      • Design Resources
      • Literature
      • Getting Started
    • Cyclone II
      • Overview
      • Design Utilities
      • Features
      • Literature
    • Cyclone
      • Overview
      • Design Utilities
      • Features
      • Literature
  • CPLDs
    • About MAX Series
    • MAX II (and G, Z)
      • Overview
        • Architecture
        • Power
        • Unique Features
      • Applications
      • Design Resources
      • Literature
      • Getting Started
    • MAX 3000A
      • Overview
      • Design Utilities
      • Features
      • Literature
  • ASICs
    • About HardCopy Series
    • HardCopy IV (E and GX)
      • Overview
        • Power
        • SEU
        • Performance
      • Transceivers
      • End Markets & Applications
      • Literature
      • Getting Started
    • HardCopy III
      • Overview
        • Architecture
        • Power
        • SEU
        • Performance
      • End Markets & Applications
      • Literature
      • Getting Started
    • HardCopy II
      • Overview
        • Power
        • SEU
        • Performance
      • End Markets & Applications
      • Literature
      • Getting Started
  • Device-Specific Offerings
    • RoHS Compliant
      • Packaging Literature
    • Extended Temperature
    • Enhanced Temperature
    • Military Temperature
  • Configuration Devices
    • Enhanced Configuration
      • Overview
      • Design Utilities
      • Features
      • Literature
    • Serial Configuration
      • Overview
      • Design Utilities
      • Features
      • Literature
  • Mature Products
    • Product Listing
    Please give us feedback
    Products | End Markets | Technology | Training | Support | About Altera | Buy Online
    Jobs | Investor Relations | Contact Us | Site Map | Privacy | Legal Notice
    Copyright © 1995-2010 Altera Corporation. All Rights Reserved.
    Altera Forum
    Altera
    Forum
    Twitter
    Twitter
    RSS
    RSS
    Facebook
    Facebook
    Flickr
    Flickr
    YouTube
    YouTube
    Email Updates
    Email
    Updates