MAX II Family Questions and Answers
The following are the questions most frequently asked about Altera® MAX® II CPLDs.
General
Q. What is the MAX II device family?
A. Altera’s MAX II family of low-cost CPLDs was the first architecture introduced that combines the best of traditional CPLD architectures with Altera's innovative FPGA look-up table (LUT) logic structure. There are three MAX II family variants, all using the same basic architecture:
- MAX II CPLDs
- MAX IIG CPLDs
- MAX IIZ CPLDs
These devices are optimized for the lowest cost-per-I/O pin and target general-purpose, low-density logic applications. Many customers use MAX II CPLDs as replacements for low-density FPGAs, ASSPs, and standard-logic devices.
Q. What design applications does the MAX II CPLD family address?
A. Altera’s MAX II CPLDs are ideal for price-sensitive, general-purpose, low-density logic applications such as interface bridging, I/O expansion, device configuration, and power-up sequencing. More information on these applications is available on the MAX II Applications page. MAX II CPLDs are also ideal for portable applications because they offer 50 percent lower cost and power than competing CPLDs.
Q. How many members are there in the MAX II CPLD family, and in what packages are they offered?
A. The MAX II CPLD family includes four members, ranging in density from 240 to 2,210 logic elements (LEs), and up to 272 user I/O pins. Devices are available with vertical migration support in low-cost thin-quad flat pack (TQFP), FineLine BGA (FBGA), and Micro FineLine BGA (MBGA) packages.
| Feature |
EPM240/G/Z |
EPM570/G/Z |
EPM1270/G |
EPM2210/G |
| LEs |
240 |
570 |
1,270 |
2,210 |
| Typical Equivalent Macrocells |
192 |
440 |
980 |
1,700 |
| Maximum User I/O Pins |
80 |
160 |
212 |
272 |
| User Flash Memory Bits |
8,192 |
8,192 |
8,192 |
8,192 |
| Speed Grades |
3, 4, 5
6, 7 (5)
|
3, 4, 5
6, 7 (5)
|
3, 4, 5 |
3, 4, 5 |
| Available Packages (1), (2) |
68-pin MBGA (5)
100-pin BGA (3)
100-pin MBGA (4)
100-pin TQFP
|
100-pin BGA (3)
100-pin MBGA (4)
100-pin TQFP
144-pin TQFP
144-pin MBGA (5)
256-pin BGA (3)
256-pin MBGA (4)
|
144-pin TQFP
256-pin BGA (3)
256-pin MBGA (4) |
256-pin BGA
324-pin BGA (3) |
Notes:
- All packages support vertical migration across all densities.
- 100-pin BGA, 100-pin MBGA, and 256-pin MBGA packages available on 3.3-V/2.5-V devices in lead-free versions only; 1.8-V device support in these packages is coming soon.
- FineLine BGA package (1.0-mm pitch).
- Micro FineLine BGA package (0.5-mm pitch).
- Only available in the MAX IIZ family.
Q. How do MAX II device ordering codes relate to their respective densities?
A. The MAX II device ordering codes are based on the number of available LEs in the device. All MAX II CPLD ordering codes begin with EPM. The digits that follow indicate the number of LEs in that device.
Q. How are "macrocell equivalents" related to LEs?
A. There is no standard conversion ratio between LEs and macrocells, but based on empirical data extracted from hundreds of customer designs, Altera determined the typical "equivalent macrocell" ratio to be approximately 1.3 LEs per macrocell.
Q. On what process technology is the MAX II CPLD family based?
A. The MAX II device family is based on a cost-optimized 1.8-V, 0.18-µm, six metal-layer flash process from Taiwan Semiconductor Manufacturing Company (TSMC).
Q. When will MAX II CPLDs be available?
A. All MAX II and MAX IIG CPLDs are available now and shipping in high volumes. MAX IIZ CPLDs will begin production shipments in the first half of 2008.
Q. What MAX II development kits are available?
A. Altera currently recommends two low-cost development kits shown in the table below.
Contact your local Altera sales representative for updates on MAX IIZ kits.
Comparisons
Q. What is the difference between MAX II, MAX IIG, and MAX IIZ CPLDs?
A. The main differences between the MAX II variants are the necessary supply voltages required to power the device as well as the power consumption specifications.
|
Feature
|
MAX II Device |
MAX IIG Device |
MAX IIZ Device |
| Product Lines |
EPM240
EPM570
EPM1270
EPM2210
|
EPM240G
EPM570G
EPM1270G
EPM2210G
|
EPM240Z
EPM570Z
|
| Supply Voltages |
3.3 V and 2.5 V |
1.8 V |
1.8 V |
| Static Power |
 |
|
Industry best |
| Dynamic Power |
Industry best |
Industry best |
Industry best |
Q. How does the MAX II CPLD family compare to existing MAX CPLD families?
A. Both device families are non-volatile and instant-on. The MAX II families are half the cost, consume one-tenth the power, and deliver four times the density of the MAX device family. The MAX device family is built on a macrocell-based architecture, while the MAX II device family is built on a LUT-based architecture.
Q. How does the MAX II CPLD family compare to the Cyclone® device family?
A. The MAX II and Cyclone device families were built to address different applications. The largest MAX II device offers 2,210 LEs, and the smallest Cyclone device offers 2,910 LEs. The MAX II family consists of non-volatile and instant-on devices, while Cyclone devices use a separate device for configuration. Despite these differences, there is an overlap in the number of I/O pins available in the MAX II and Cyclone devices. In addition, while the two device families are comparable in cost per LE, MAX II CPLDs will always be lower in cost per I/O pin.
Power
Q. How does the MAX II CPLD family's power consumption compare with prior generation MAX devices?
A. The MAX II family’s power consumption is approximately one-tenth that of the previous-generation MAX CPLDs.
Q. What is the standby current specification?
A. The standby current specification assumes the input voltage is zero (GND), there is no load, and no inputs toggling.
|
Feature
|
MAX II CPLD |
MAX IIG CPLD |
MAX IIZ CPLD |
| Supply Voltages |
3.3-V and 2.5-V |
1.8-V |
1.8-V |
| Static Power (Typical) |
12 mA |
2 mA |
29 µA (EPM240Z)
32 µA (EPM570Z)
|
| Dynamic Power |
Industry best |
Industry best |
Industry best |
Q. How does the MAX II device conserve battery life for portable applications?
A. A MAX II low-power CPLD can be completely powered-down because of its superior hot-socket, power-sequence flexibility, and single power supply simplicity. More information on the power-down capability is available on the MAX II Low-Power page and the MAX II Power-Down Design Example page.
Performance
Q. How does the MAX II CPLD family's performance compare with prior generation MAX CPLDs?
A. The MAX II family’s performance is on average twice as fast as the previous-generation MAX CPLDs.
Q. How do the speed grades relate to the tpd specification?
A. The speed grades describe the relative speed of each device. The -3 is the fastest, the -4 is the medium, and the -5 is the slowest speed grade. The "fastest tpd1" specification in the MAX II Device Handbook correlates to the fastest commercial speed grade, which is a corner-to-corner delay path through the device.
Q. MAX II CPLDs and Stratix® II FPGAs have the same speed grades. Are the performance specifications the same?
A. For both the MAX II and Stratix II families, the -3 speed grade is the fastest, -4 is the medium, and -5 is the slowest. Even though the speed grade nomenclature is the same, the performance specifications are not.
Packaging
Q. Are the MAX II devices pin-compatible with prior generation MAX CPLDs?
A. No. MAX II CPLDs are based on a completely new architecture and are, therefore, not pin-compatible with Altera’s MAX 7000 or MAX 3000 device families.
Q. Why are fewer user I/O pins available when you migrate to a higher-density device in the same package?
A. Each MAX II CPLD family member is optimized for the highest possible number of I/O pins in the lowest density device for a given package. Because of higher LE counts, high-density members require a greater number of power and ground pins to operate correctly. For any given package, therefore, the number of available user I/O pins must be reduced when a denser device is used.
Features
Q. What is the power-on time for this instant-on family?
A. The smallest MAX II device (EPM240) powers-on in less than 200 microseconds, from the time the supply voltage meets the minimum VCC. The EPM570 and EPM2210 devices power-up in less than 300 microseconds. The largest MAX II device (EPM2210) powers-on in less than 450 microseconds, from the time the supply voltage meets the minimum VCC.
Q. What is the difference between the user flash memory and the configuration flash memory?
A. The user flash memory allows you to integrate discrete serial or parallel non-volatile storage onto MAX II CPLDs. The configuration flash memory, which is not user accessible, is employed internally to store the programmed design information that is subsequently loaded into the programmable logic.
Q. Can MAX II devices be in-system programmed?
A. Yes. The MAX II CPLDs support in-system programmability through the JTAG ports using .pof , JamTM STAPL, .svf , or IEEE 1532 files.
Q. Are there any phase-locked loops (PLLs) available in MAX II CPLDs?
A. No. There are no PLLs available in MAX II CPLDs. The die size, power requirements, and clock pins required for PLLs would have increased device cost above desired levels.
I/O Standards
Q. Which single-ended I/O electrical standards does the MAX II CPLD family support?
A. MAX II CPLDs support a variety of single-ended I/O standards, including LVTTL, LVCMOS, and PCI. MAX II CPLDs also support a programmable slew rate and drive strength control for certain I/O standards.
Q. Does the MAX II CPLD family support hot socketing?
A. Yes. The VCCIO and VCCINT power pins can be powered-up in any order. In addition, signals can be driven into the MAX II devices before and during power-up (and power-down) without damaging the device, because device I/O pins do not source or sink more than 300 µA of DC current during these operations.
Q. Which I/O voltages does the MAX II CPLD family support?
A. The MAX II CPLDs have up to four I/O banks that seamlessly interface to other devices at 3.3-, 2.5-, 1.8-, and 1.5-V logic levels.
Q. Are MAX II CPLDs 5.0-V tolerant?
A. The two larger MAX II CPLDs are 5.0-V tolerant when used with an external series resistor and the on-chip PCI clamping diode. The two smaller devices are not 5.0-V tolerant.
Q. Do MAX II CPLDs support PCI?
A. The two largest MAX II CPLDs support 66-MHz, 32-bit PCI.
Software and Intellectual Property
Q. Which versions of the Quartus® II design software support MAX II CPLDs?
A. All MAX II CPLDs are supported by the Quartus II Web Edition software version 4.0 or higher, which you can download for free. The full version of the Quartus II design software version 4.0 or higher, available through Altera’s subscription program, also supports all MAX II devices. Programming file generation for the MAX II CPLDs will also be supported in a subsequent software release.
Q. Does the MAX+PLUS® II design software support MAX II CPLDs?
A. No. MAX II CPLDs are supported in the Quartus II design software, versions 4.0 or higher.
Q. Which third-party tools support MAX II CPLDs?
A. Synthesis and simulation tools from leading EDA vendors Mentor Graphics® (Precision 2003C) and Synplicity (Synplify 7.5.1) support the MAX II CPLD family to ensure the highest quality design implementation.
Q. Which intellectual property (IP) cores are available for MAX II CPLDs?
A. Altera offers a PCI core for the MAX II CPLDs. Support will also be provided for a select number of common interfacing cores, including I2 C, SPI, and UARTs.
Q. What MAX II development kits are available?
A. Altera currently recommends two low-cost development kits shown in the table below.
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