Cyclone™ II devices expand the role of FPGAs in low-cost, high-volume applications, in both new and existing FPGA markets. No longer restricted to peripheral uses, FPGAs now perform many critical processes within systems. As FPGAs are increasingly used in the datapaths within systems they must be able to interface to external memory devices when storage requirements exceed the abundant on-chip memory resources.
Altera built on the tremendous success of the Cyclone device family and worked with leading memory vendors to ensure users can connect the very latest memory devices to Cyclone II FPGAs. Cyclone II devices are designed to communicate with double data rate (DDR), DDR2, single data rate (SDR) SDRAM devices, and quad data rate (QDRII) SRAM devices through a dedicated interface that ensures fast and reliable data transfer at up to 668 megabits per second (Mbps). Designers can incorporate SDRAM and SRAM devices into their systems in minutes working with Cyclone II-optimized, off-the-shelf intellectual property (IP) controller cores. Table 1 summarizes the Cyclone II external memory interfaces support.
| Table 1: External Memory Interfaces Support in Cyclone II Devices | ||||
| Memory Technology | I/O Standard | Maximum Bus Width | Maximum Clock Speed | Maximum Data Rate |
|---|---|---|---|---|
| SDR SDRAM | 3.3-V LVTTL | 72 bits | 167 MHz | 167 Mbps |
| DDR SDRAM | 2.5-V SSTL Class I, II |
72 bits | 167 MHz | 334 Mbps |
| DDR2 SDRAM | 1.8-V SSTL Class I, II |
72 bits | 167 MHz | 334 Mbps |
| QDRII SRAM | 1.8-V HSTL Class I, II |
36 bits | 167 MHz | 668 Mbps |
Memory Devices
DDR SDRAM devices have recently become very popular primarily because of their low power consumption, relatively low cost, and high bandwidth. Because data transactions occur on both edges of the clock, DDR SDRAM devices effectively double total data bandwidth over slower SDR architectures. DDR SDRAM devices have penetrated markets beyond the personal computer (PC) space and are now widely used in a broad spectrum of applications ranging from networking and communications to set-top boxes and home entertainment systems. DDR2 memory retains these features and offers faster clock rates and performance. Industry experts believe that DDR2 will be the next dominant DRAM type for many years to come because of larger densities and because DDR2 has been adopted as personal computer (PC) main memory.
Quad data rate (QDRII) SRAM devices enable system designers to maximize data throughput, primarily in communication applications at data rates up to 167 MHz. The QDRII architecture features two data ports (input and output) operating twice per clock cycle to deliver a total of four data instructions per cycle. The resulting performance increase is particularly valuable in bandwidth and latency intensive applications such as main memory for look-up tables, linked lists and controller buffer memory.
More information about these memory device types and Altera® support for them is available on the Memory System Solutions web page.
Interface Technical Details
Cyclone II devices have been designed for reliable data transfer to and from external memory devices at high speed. The key to high-speed interfacing is to include dedicated I/O features to ensure that all timing requirements are satisfied and performance is maximized with minimum design effort.
Each Cyclone II device is equipped with optimized I/O pins to interface with DDR/DDR2, SDR SDRAM, and QDRII SRAM devices. Each I/O bank features up to two sets of interface signal pins and each set contains a single data strobe (DQS) pin and associated data (DQ) pins. These pins are designed for high-speed data transfer with an external memory device using the SSTL-18 Class I/II, SSTL-2 Class I/II, and HSTL Class I/II I/O standards. Up to 72 DQ pins are available per device with corresponding DQS pins, which support a single dual-inline memory module (DIMM) with 64-bit data and error correction.
The dedicated data strobe DQS circuitry shifts the DQS signal for optimized clock and data alignment during read cycles. The circuitry does not use external printed circuit board (PCB) trace delays and it minimizes clock skew between strobe DQS and data DQ signals. This ensures high-speed DDR memory timing requirements can be met reliably while saving PCB cost. Figure 1 shows a typical interface between Cyclone II FPGAs and DDR memory devices. Data pins are routed on the board in groups. Clock strobes are routed along with the data groups, one per group. The memory controller IP on Cyclone II devices generates the address and control signals and sends them to the off-chip memory. Cyclone II devices also generates the system clock.
Figure 1: Typical Interface between Cyclone II FPGA & DDR Memory
Notes to Figure 1:
- Bi-directional data and strobe.
- Strobe routed with data group.
- System clock optionally generated by PLL.
Read Operations
Figure 2 shows read operations from a memory device for a single data bit. The DQS signal is center-aligned with the incoming DQ signal and fed to the device's global clock network. The DQ signal is captured on both edges of the clock using FPGA registers and synchronized with the system clock using a second set of positive-edge-triggered core registers.
Figure 2: External Memory Device Read Operation
Write Operations
Figure 3 shows write operations to memory devices for a single data bit. The DQS signal is sent to the memory device 90 degrees out-of-phase with the transmitted data. Output-enable logic is used to meet associated pre-amble and post-amble timing requirements.
The DQ signal is sent to the memory device on both edges of the in-phase system clock, using a set of logic registers and an output multiplexer that toggles between the data A and data B signals.
Figure 3. External Memory Device Write Operation
More information about the external memory interface in Cyclone II devices is available in the Cyclone II Device Family Data Sheet (PDF) in the Cyclone II Device Handbook.
IP Optimized for Cyclone II Devices
Altera offers fully customizable IP megafunction controller cores developed and tested by Altera and Altera Megafunction Partners Program (AMPP) partners on the IP MegaStore web site. Altera also offers several memory controller design examples for users designing their own custom memory interfaces. These megafunctions allow designers to quickly and easily incorporate interfaces to the latest memory technologies into their Cyclone II designs using an intuitive graphical user interface (GUI) from within the Quartus® II software. This process automatically configures all the dedicated external memory support features of Cyclone II devices. Where time-to-market is critical, memory controller IP enables designers to focus on their products’ functionality.
