Cyclone II I/O Support
Cyclone™ II devices support a variety of single-ended and differential I/O standards and a wide array of interfaces and protocols that give system designers flexibility in designing their systems. Altera supports these I/O standards, interfaces, and protocols with parameterized parameterized blocks of intellectual property (IP) from Altera and Altera Megafunction Partners Program (AMPPSM) partners to reduce design and test time where applicable.
Single-Ended I/O Standards
Cyclone II devices support single-ended I/O standards such as LVTTL, LVCMOS, SSTL-2, SSTL-18, HSTL-18, HSTL-15, PCI, and PCI-X to interface with other on-board devices. Single-ended I/O standards are critical when working with advanced memory devices such as double-data rate (DDR and DDR2) SDRAM and QDRII SRAM devices. Table 1 lists the single-ended I/O standards and target performance supported in Cyclone II devices.
| Table 1. Cyclone II Device Single-Ended I/O Standard Support |
| I/O Standard |
Performance |
Typical Application |
| 3.3-V/2.5-V/1.8-V LVTTL |
167 MHz |
General Purpose |
| 3.3-V/2.5-V/1.8-V/1.5-V LVCMOS |
167 MHz |
General Purpose, PCI Express PIPE (1) |
| 3.3-V PCI |
66 MHz |
Personal Computer (PC), Embedded |
| 3.3-V PCI-X |
100 MHz |
PC, Embedded |
| 2.5-V/1.8-V SSTL Class I |
167 MHz |
Memory |
| 2.5-V/1.8-V SSTL Class II |
133 MHz/125 MHz |
Memory |
| 1.8-V/1.5-V HSTL Class I |
167 MHz |
Memory |
| 1.8-V/1.5-V HSTL Class II |
100 MHz |
Memory |
Note to Table 1:
- Supports connection to external PHY devices using 1.5-V or 1.8-V LVCMOS to implement the PCI Express PIPE protocol.
Differential I/O Standards
Compared to single-ended I/O standards, differential signaling in Cyclone II devices provides better noise immunity, lower electromagnetic interference (EMI) generation, and reduced power consumption. Table 2 lists the differential I/O standards and target performance supported in Cyclone II devices.
| Table 2. Cyclone II Device Differential I/O Standard Support |
| I/O Standard |
Performance |
Typical Application |
| LVDS |
805 Mbps Rx (1), 622 Mbps Tx (2) |
Chip-to-Chip, Backplane Driver |
| mini-LVDS |
170 Mbps Tx |
General Purpose |
| RSDS (3) |
170 Mbps Tx |
General Purpose |
| LVPECL |
150 MHz |
Clock Inputs Only |
| Differential HSTL (4) |
167 MHz |
Memory |
| Differential SSTL |
167 MHz |
Memory |
Notes to Table 2:
- Rx = receive
- Tx = transmit
- RSDS = reduced swing differential signaling
- HSTL = high-speed transceiver logic
Figure 1 shows the LVDS interface in Cyclone II devices.
Figure 1. LVDS Interface in Cyclone II Devices
Figure 2 shows the mini-LVDS interface in Cyclone II devices.
Figure 2. RSDS & mini-LVDS Interface in Cyclone II Devices
Note to Figure 2:
- RS and RP values are dependent on device characterization. Estimated values are RS = 120Ω and RP = 170Ω. The resistor values chosen should satisfy the following equation:
[RS x (RP/2)] / [RS + (RP/2)] = 50Ω.
Table 3 lists the number of differential data channels and target performance supported in Cyclone II devices.
| Table 3. Number of Differential Channels & Performance per Cyclone II Device |
| Device |
Package |
Number of Differential Channels (1) |
LVDS Performance |
RSDS & mini-LVDS Performance |
| Transmit |
Receive |
Transmit |
| EP2C5 |
144-pin TQFP (2) |
33 |
622 Mbps |
805 Mbps |
170 Mbps |
| 208-pin PQFP (3) |
58 |
622 Mbps |
805 Mbps |
170 Mbps |
| 256-pin FBGA (4) |
55 |
622 Mbps |
805 Mbps |
170 Mbps |
| EP2C8 |
144-pin TQFP |
31 |
622 Mbps |
805 Mbps |
170 Mbps |
| 208-pin PQFP |
55 |
622 Mbps |
805 Mbps |
170 Mbps |
| 256-pin FBGA |
77 |
622 Mbps |
805 Mbps |
170 Mbps |
| EP2C20 |
208-pin PQFP |
40 |
622 Mbps |
805 Mbps |
170 Mbps |
| 256-pin FBGA |
56 |
622 Mbps |
805 Mbps |
170 Mbps |
| 484-pin FBGA |
132 |
622 Mbps |
805 Mbps |
170 Mbps |
| EP2C35 |
484-pin FBGA |
135 |
622 Mbps |
805 Mbps |
170 Mbps |
| 672-pin FBGA |
205 |
622 Mbps |
805 Mbps |
170 Mbps |
| EP2C50 |
484-pin FBGA |
122 |
622 Mbps |
805 Mbps |
170 Mbps |
| 672-pin FBGA |
193 |
622 Mbps |
805 Mbps |
170 Mbps |
| EP2C70 |
672-pin FBGA |
164 |
622 Mbps |
805 Mbps |
170 Mbps |
| 896-pin FBGA |
261 |
622 Mbps |
805 Mbps |
170 Mbps |
Notes to Table 3:
- The number of differential channels is subject to change.
- TQFP = thin quad flat pack.
- PQFP = plastic quad flat pack.
- FBGA = FineLine BGA® package.
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