Cyclone II Power Comparison—1/2 the Power of Competing 90-nm Low-Cost FPGAs
Compared to competing 90-nm low-cost FPGAs, CycloneTM II devices offer:
The Cyclone II Total Advantage
- #1 in Low Power—Half the power of competing 90-nm low-cost FPGAs.
- #1 in Price—No price premiums for lower power. Competing 90-nm low-cost FPGAs have a price premium to obtain lower power devices.
- #1 in Performance—60 percent higher performance than competing 90-nm low-cost FPGAs. Obtain low power and high performance from a single FPGA.
1/2 the Total Power
Power data show that Cyclone II FPGAs consume half the total power of Spartan-3 and Spartan-3L FPGAs. This is true even when comparing worst-case silicon at 85°C in Cyclone II FPGAs versus typical silicon in Spartan-3 and Spartan-3L devices at 25°C. If the Spartan-3 Web Power Tool version 4.1.1 supported worst-case conditions (process and temperature), the Cyclone II power advantage would be even greater.
The Figure 1 comparison shows the total power consumption between the three product families, all with equivalent resource utilization. Power estimation tools were used for Altera® and Xilinx products: the Cyclone II PowerPlay early power estimator version 1.0 and the Spartan-3 Web Power Tool version 4.1.1 power estimation tools, respectively. See Tables 1, 2, and 3 for more information on the comparison.
Figure 1. Cyclone II vs. Spartan-3 & Spartan-3L Total Power Consumption Comparison
Table 1 below shows the process, voltage, and temperature conditions for the comparison in Figure 1.
| Table 1. Process, Voltage & Temperature Conditions |
| Product Family |
Process
|
Voltage
|
Junction Temperature (Tj) |
|
Cyclone II
|
Worst-Case Process
|
Core = 1.2 V
I/O = 3.3 V
|
85°C |
| Spartan-3 & Spartan-3L |
Typical Process (1)
|
Core = 1.2 V
I/O = 3.3 V
Auxiliary (2) = 2.5 V
|
25°C (3) |
Notes:
- Worst-case process in the Spartan-3 Web Power Tool version 4.1.1 is not supported.
- Unlike Cyclone II devices, Spartan-3 and Spartan-3L devices require an additional auxiliary power supply at 2.5 V.
- Temperature variation in the Spartan-3 Web Power Tool version 4.1.1 is not supported, results shown for 25°C.
Device Resources & Conditions
Table 2 below lists the device resources utilized for the comparison in Figure 1.
Benchmarks were based on the following criteria:
-
Operating frequency used for each design was 150 MHz.
-
Routing used for each design was medium routing.
-
Equivalent device densities used between Altera and Xilinx.
-
Spartan-3E not supported in any Xilinx tools. The Spartan-3E typical power numbers are higher than those of Spartan-3 and Spartan-3L devices.
| Table 2. Device Resources Used in Total Power Measurements |
|
Design
Number
|
Devices
|
Look-Up Tables (LUTs)
|
Flipflops
(FFs)
|
Embedded RAM
|
Hard Multipliers
|
Phase-locked loops (PLLs)/Digital Clock Managers (DCMs)
|
I/Os
|
|
1
|
EP2C5
XC3S200
|
3,500
|
1,750
|
119 Kb
|
10
|
2
|
50
|
|
2
|
EP2C8
XC3S400
|
7,000
|
3,500
|
165 Kb
|
15
|
2
|
70
|
|
3
|
EP2C20
XC3S1000L
|
15,000
|
7,500
|
230 Kb
|
20
|
2
|
150
|
|
4
|
EP2C35
XC3S2000
|
25,000
|
12,500
|
480 Kb
|
40
|
2
|
200
|
|
5
|
EP2C50
XC3S4000L
|
40,000
|
20,000
|
590 Kb
|
95
|
2
|
250
|
|
6
|
EP2C70
XC3S5000
|
50,000
|
25,000
|
1,130 Kb
|
100
|
2
|
400
|
Table 3 lists the device conditions for the comparison in Figure 1.
| Table 3. Conditions Used in Total Power Measurements |
|
Resource
|
Conditions
|
Notes
|
|
LUT/FF
|
12.5 Percent Toggle Rate
|
1 LUT + 1 FF
|
|
RAM
|
Dual Port, 50 Percent Write on Port A, 50 Percent Read on Port B
|
-
|
|
Multipliers
|
18x18 Multipliers
|
Set High Toggle for Xilinx
Set 50 Percent Toggle for Altera
|
|
I/O
|
50/50 Percent I/Os, 30 Percent Toggle Rate, 100 Percent Output Enable, 3.3V LVCMOS 12mA, 10 pF
|
-
|
|
Clock Routing
|
Proportional to Amount of Logic
|
Missing in Xilinx Model
|
1/2 the Static Power
Cyclone II devices consume less static power than Spartan-3L FPGAs and half the static power of Spartan-3 FPGAs. This is true when comparing worst-case process in the devices. In addition, the Cyclone II PLLs consume approximately one-tenth the static power of Spartan-3 and Spartan-3L DCMs.
Utilizing the Cyclone II PowerPlay early power estimator version 1.0 and the quiescent supply current characteristics from Module 3 v1.5 of the Spartan-3 data sheet and the Spartan-3L v1.0 data sheet, the comparison in Figures 2 and 3 below show the worst-case static power consumption between Cyclone II, Spartan-3, and Spartan-3L devices.
Power varies on silicon with process, voltage, and temperature. For accurate and reliable power estimation, it is important for FPGA companies to specify worst-case process. Maximum temperature specifications in power estimation tools are also critical in your power estimations due to the relationship of power consumption to temperature.
Benchmarks for Figure 2 were based on the following criteria:
- Worst-case process not specified in Module 3 v1.5 of the Spartan-3 data sheet. Worst-case numbers for Spartan-3 are based on Xilinx’s guidance of using a 2.0 factor for worst-case process on Spartan-3 device’s 1.2 V power rail. The lower limit of the worst-case to typical process variation shown represents Spartan-3 typical process.
- Static power numbers for Spartan-3 devices were calculated by multiplying the quiescent supply current characteristics from Module 3 v1.5 of the Spartan-3 data sheet by the nominal three power supplies and summing the results.
- Xilinx omits static power numbers at 85°C for Spartan-3 XC3S2000, XC3S4000, and XC3S5000 in the Spartan-3 data sheet v1.5, the Spartan-3 Web Power Tool version 4.1.1, and XPower. Assumes linear power variation across device densities for densities above ~26,000 equivalent logic elements (represented by dotted line).
Figure 2. Cyclone II vs. Spartan-3 Static Power Consumption Comparison
Note:
-
PLL and DCM comparison not represented in Figure 2.
Benchmarks for Figure 3 were based on the following criteria:
- Worst-case process not specified in the Spartan-3L data sheet v1.0. Worst-case numbers for Spartan-3L are based on Xilinx’s guidance of using a 2.0 factor for worst-case process on Spartan-3L device’s 1.2 V power rail. The lower limit of the worst-case to typical process variation shown represents Spartan-3L typical process.
- The Spartan-3L device family only supports three device densities and one speed grade. Low power is available in all Cyclone II densities and speed grades.
- Static power numbers for Spartan-3L devices were calculated by multiplying the quiescent supply current characteristics from the Spartan-3L v1.0 data sheet by the nominal three power supplies and summing the results.
Figure 3. Cyclone II vs. Spartan-3L Static Power Consumption Comparison
Note:
-
PLL and DCM comparison not represented in Figure 3.
1/2 the Dynamic Power
Power data show that Cyclone II devices consume better than half the dynamic power of competing 90-nm low-cost FPGAs for core logic. The Figure 4 comparison below shows the dynamic power consumption between the three product families using equivalent resource utilization. The Cyclone II PowerPlay early power estimator version 1.0 and the Spartan-3 Web Power Tool version 4.1.1 power estimation tools were used for the Altera and Xilinx devices respectively. The process, voltage, and temperature conditions shown in Table 1 were applied to obtain the results.
Figure 4. Cyclone II vs. Spartan-3 & Spartan-3L Dynamic Power Consumption Comparison
Zero Inrush Current
Cyclone II devices do not cause any inrush current spike during power up; the current rises monotonically during power up, which, in turn, eliminates the need for special power-up requirements. During device power up, the current provided by a power supply to a Cyclone II FPGA will monotonically increase to its steady state level at ICCINT standby. Only static power is consumed at ICCINT standby levels. Since Cyclone II device current monotonically increases during power-up, its power-up requirement is the same as its static power.
Unlike Cyclone II devices, Spartan-3 and Spartan-3L devices have some limitations to guarantee zero in-rush current. Spartan-3 devices require a specific power-up sequence, forcing you to apply the extra auxiliary voltage before the core and the I/O voltages. Cyclone II devices do not have any power-up sequence requirements.
Hot-Socketing Support
Like many other Altera devices, Cyclone II FPGAs are fully "hot socketable:" you can insert or remove a board during system operation without causing negative effects to the system or the board. This is also referred to as "hot swapping" or "hot plug-in."
To be considered a hot-socketable device, the device must meet three criteria:
- It can be driven before power up without any damage
- It does not drive out before or during power up
- External input signals to the device’s I/O pins do not power its VCCIO or VCCINT power supplies through the device’s internal paths.
Spartan-3, Spartan-3L, and Spartan-3E do not support hot socketing.
To find out more about the advantages of the on-chip hot-socketing support in Altera devices, refer to the white paper, Altera Hot-Socketing & Power-Sequencing Advantages (PDF). For detailed characterization data, refer to the white paper, Hot-Socketing & Power-Sequencing Feature & Testing for Altera Devices (PDF).
Fewer Power Supplies
Cyclone II devices require fewer power supplies than Spartan-3, Spartan-3L, and Spartan-3E devices.
This feature gives engineers a number of advantages.
- Board Size—Free up board space using less power supplies.
- Board Cost—Spend less on extra power supplies and board design costs.
- Board Complexity—Use fewer power planes and simplify power sequencing issues.
Low Power by Design
Cyclone II devices are manufactured on TSMC’s 90-nm process technology. Altera worked closely with TSMC to optimize the process node for low power consumption without sacrificing performance. Table 4 shows some of the features pertinent to low power applications. The table also compares these techniques used in Cyclone II FPGAs versus competing products.
| Table 4. Low Power Features for Low-Cost FPGAs |
|
Low Power Features
|
Cyclone II
|
Spartan-3
|
Spartan-3L
|
Spartan-3E
|
Customer Benefit
|
|
Lower Core Voltage at 1.2 V
|
Yes
|
Yes
|
Yes
|
Yes
|
Lower static and dynamic power with reduced voltage.
|
|
Low-k Dielectric
|
Yes
|
No
|
No
|
No
|
Lowers dynamic power by 10 percent and increases performance.
|
|
Zero
Inrush Current
|
Yes
|
No
|
No
|
Unknown
|
No power-up sequencing requirements, and no additional board complexity.
|
|
Hot-Socketing
|
Yes
|
No
|
No
|
No
|
Capable of inserting or removing a board during system operation without causing negative effects to the system or the board.
|
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