The Cyclone II Power Advantage—1/2 the Power of Competing 90-nm Low-Cost FPGAs
Figure 1. Worst-Case Total Power Comparison
Continuing its market leadership in the low-cost FPGA space, Cyclone II devices are the industry’s lowest-cost, lowest-power 90-nm FPGAs available today -consuming as little as 12 mW of static power. Built from the ground up for low cost and optimized for low power consumption, Cyclone II devices consume half the power of competing 90-nm low-cost FPGAs.
Compared to competing 90-nm low-cost FPGAs, Cyclone II devices offer:
To learn how Cyclone II FPGAs compare with competing FPGAs, please visit the Cyclone II Power Comparison.
Altera® has the most accurate and complete power management design tools. Unlike other competing vendors that offer only typical silicon power estimates for their low-cost families, Altera additionally offers 85° C and worst-case silicon power estimates throughout its tool suite, essential for reliable designs. Altera offers the following resources to give engineers the most accurate and reliable information on power:
Altera Techniques for Lowering Power Consumption in Silicon
There are many techniques that can be employed when reducing power in silicon. Table 1 describes some techniques used in Cyclone II FPGAs.
| Table 1. Silicon Design & Process Techniques for Reducing Power Consumption at 90 nm |
| Technique |
Power Benefit |
Specific Effects |
| Decrease Core Voltage |
Total Power Reduced |
- Reduces leakage current
- Reduces switching current
|
| Increase Vt (Threshold Voltage) |
Static Power Reduced |
- Reduces leakage current
- Reduces transistor performance
- Applied for non-speed-critical paths
|
Increase
Transistor Length |
Static Power Reduced |
- Reduces leakage current
- Reduces transistor performance
- Applied for non-speed-critical paths
- Reduces power variance across process
|
Process Changes:
FSG to Low-K Dielectric |
Dynamic Power Reduced |
- Reduces dynamic power ~10 percent
- Increases performance ~10 percent
- Proven at TSMC with 0.13-micron process
- Used in 100 percent of TSMC 90-nm products
|
| Lower I/O Pin Capacitance |
Dynamic Power Reduced (I/O) |
- Reduces dynamic power
- Increases I/O performance
- Improved signal integrity within device
|
| Power Efficient Clocking Structure |
Dynamic Power Reduced |
- Automatic ability to shut down parts of clock network allows for significant reduction in dynamic power
- Wide range of clock resource types allow for power-optimized clock selection
|
Manufacturers must intelligently employ the techniques described in Table 1 to optimize performance while minimizing power consumption in silicon. Altera took these steps to help keep silicon power consumption as low as possible without compromising customer performance requirements or manufacturability. Altera FPGAs generate less heat and consume less system power.
Related Links
|
Literature
> 
Next Steps