Altera's Cyclone II FPGA Interfaces & Protocols Support

Cyclone^TM II devices support serial, bus, and network interfaces, as well as a wide range of communications protocols. These interfaces and protocols are commonly used in many industrial, communications, and an increasing number of consumer applications.

• PCI Express
• PCI
• PCI-X
• SDRAM and SRAM Interfaces
• Ethernet Protocols
• Consumer Digital Display Standards
• Serial Bus Interfaces
• Communications Protocols

Altera offers a variety of intellectual property (IP) cores for these protocols that are optimized for the Cyclone II FPGA architecture.

PCI Express

PCI Express is rapidly establishing itself as the successor to PCI, providing higher performance, increased flexibility, and scalability for next-generation systems without increasing costs, all while maintaining software compatibility with existing PCI applications. You can now easily design high volume, low-cost PCI Express x1 solutions today featuring:

• Cyclone II FPGA
  • 60% higher performance and 1/2 the power consumption of competing 90-nm FPGAs
  • Supported by free Quartus^® II Web Edition Software 
• Altera^® PCI Express Compiler x1 MegaCore^® function 
• External PCI Express transceiver/PHY
  • A preset PIPE configuration for use with the Texas Instruments x1 PCI Express Physical Layer transceiver (XIO1100) is included with the Altera PCI Express Compiler x1 MegaCore function

Start Your Low-Cost PCI Express Design Now
Learn more

PCI

The PCI local bus is a high-performance 32-bit or 64-bit bus with multiplexed address and data lines. The bus provides a processor-independent data path between highly integrated peripheral controller components, peripheral add-in boards, and processor/memory systems. The Cyclone II PCI system interface is designed to be fully compliant with the 3.3-V PCI Local Bus Specification (Rev. 2.2) and meets 64-bit/66-MHz operating frequency and timing requirements. The I/O elements in Cyclone II devices are specifically designed to meet the strict PCI set-up and hold time requirements. To provide maximum flexibility, each input signal can go through two separate delay paths feeding different areas of the device (Figure 1).

Figure 1. Cyclone II Device I/O Element

Note:

1. The PCI clamp diode is available on the left and right side of the device

PCI-X

Since the introduction of the 66-MHz PCI Local Bus Specification in 1994, bandwidth requirements of peripheral devices have grown steadily. The preferred approach to moving beyond today’s PCI Local Bus Specification is to enhance it. PCI-X enables the design of systems and devices that can operate at speeds significantly higher than today’s specification allows. Just as importantly, it provides backward compatibility by allowing devices to operate at conventional PCI frequencies and modes when installed in conventional systems. This high degree of backward compatibility enables the easy migration of systems and devices to bandwidth in excess of 1 gigabit per second (Gbps). Cyclone II FPGAs meet both the 33-MHz and the 66-MHz protocols and timing requirements of PCI and the timing requirements up to 100 MHz of PCI-X.

Table 1 lists the required PCI bus operation modes when devices of various PCI standards are used.

Table 1. PCI and PCI-X Interoperability
Device(s) on Bus	Operation Mode of Bus
One or More 33-MHz PCI Device	Conventional 33-MHz Mode
Only 66-MHz PCI Devices	Conventional 33-MHz or 66-MHz Mode
Only PCI-X Devices	PCI-X Mode
One or More PCI-X 66-MHz Device	Maximum Clock Frequency of 66 MHz
Only PCI-X 100-MHz Devices	Maximum Clock Frequency of 100 MHz

SDRAM and SRAM Interfaces

SDRAM and SRAM devices are used broadly in applications including PCs, consumer electronics, communications, and networking for data storage. Cyclone II devices are designed to communicate with single data rate (SDR) and double data rate (DDR) and DDR2 SDRAM, as well as QDRII SRAM devices through a dedicated interface that ensures fast, reliable data transfer at up to 668 megabits per second (Mbps). Details are available in the external memory interfaces section of this website.

10/100 and Gigabit Ethernet

Ethernet is the most widely used local area network (LAN) access method and is defined by the IEEE 802.3 standard. Cyclone II devices can be used to implement the Ethernet media access controller (MAC) and can be interfaced with physical layer (PHY) devices at a maximum bandwidth of 10 Mbps, 100 Mbps, or 1 Gbps.

Together with Cyclone II device-optimized IP cores, designers can integrate an Ethernet MAC function into a Cyclone II device in minutes.

Consumer Digital Display Standards–FPD, Flat Link, RSDS and mini-LVDS

Flat panel display (FPD) link is a National Semiconductor-defined LVDS-based link between a host panel and display panel in an LCD monitor and television platform. Cyclone II devices are predominantly placed at the receive-end of the FPD link to meet the maximum data rate requirement of 805 Mbps. A single FPD link channel consists of four LVDS data pairs and a source-synchronous clock pair; Cyclone II devices support up to two such channels.

Flat link is a Texas Instruments-defined LVDS-based link between a host panel and display panel in an LCD monitor and television platform. This interface is similar to that of FPD link and is primarily used by Philips and Thomson. Cyclone II devices are predominantly placed at the transmit-end of the Flat Link to meet the maximum data rate requirement of 622 Mbps and can be used on the receiver-side as well.

Reduced swing differential signaling (RSDS) is a National Semiconductor-defined signaling standard primarily used for display applications with resolutions between video graphics arrays (VGAs) and ultra extended graphic arrays (UXGAs). It is a chip-to-chip protocol and links the flat-panel timing controllers to the column drivers. RSDS is a differential interface with a nominal swing of 200mV and retains the many benefits of the LVDS interface for a high-bandwidth, robust digital interface.

mini-LVDS is a Texas Instruments-defined interface similar to RSDS and meets the same needs. The requirements for mini-LVDS interfaces are identical to that of RSDS, except in the AC timing requirements. mini-LVDS assumes a center-aligned output clock.

Serial Bus Interfaces

Cyclone II devices support a variety of serial bus interfaces such as serial peripheral interface (SPI), inter-integrated circuit (I2C), IEEE 1394 standard, and universal serial bus (USB) (shown in Table 2).

Table 2. Serial Bus Interface Support in Cyclone II Devices
Protocol	SPI	I2C	IEEE 1394	USB 2.0
Maximum Bandwidth (Mbps) (1)	1	3.4	400	480

Note:

1. Maximum bandwidth is equal to or greater than the data rate.

The SPI and I2C standards can be implemented in Cyclone II devices to provide low-speed communication links between integrated circuits, processors and peripherals. The IEEE 1394 and USB standards provide connections between processors, computers, and other devices. Cyclone II devices can be used to implement the bus controllers and interface with the PHY devices. All these serial bus interfaces are typically used in price-sensitive consumer products. The Cyclone II device family provides an ideal low-cost solution for implementing the standards and custom functions in these applications.

Communications Protocols

Cyclone II devices support various communication protocols including E1, E3, T1, T3, and SONET/SDH protocols (Table 3).

Table 3. Communications Protocol Support in Cyclone II Devices
Protocol	E1	E3	T1	T3	OC-1/ STM-0	OC-3/ STM-1	OC-12/ STM-4	OC-48/ STM-16
Maximum Bandwidth (Mbps) (1)	2.048	34.368	1.544	44.736	51.84	155.52	622.08	2,488

Note:

1. Maximum bandwidth is equal to or greater than the data rate.

E1 and E3 are the European standards for digital transmission; T1 and T3 are the corresponding North American standards for digital transmissions. SONET/SDH standards provide data transmission over fiber optics. Cyclone II devices can be used to implement the framers of all these protocols and connect to the transceiver devices.

Cyclone II devices can also be used to implement the POS-PHY and UTOPIA communications interface protocols shown in Table 4.

Table 4. Communications Interface Protocol Support in Cyclone II Devices
Protocol	POS-PHY Level 2	POS-PHY Level 3	UTOPIA Level 2	UTOPIA Level 3
Maximum Bandwidth (Mbps) (1)	622	2,488	622	2,488
Bus Width	16	8/32	8/16	8/16/32

Note:

1. Maximum bandwidth is greater than the data rate.

POS-PHY and UTOPIA protocols provide physical and link layer interfaces for SONET/SDH and asynchronous transfer mode (ATM) respectively. These protocols and interfaces can be implemented in Cyclone II devices.

These communications and interface protocols are used in low-end and mid-range communications equipment. Cyclone II devices provide the performance, logic density, and system features required to support these applications.