Cyclone III Device Family Architecture
The Cyclone® III family of 65-nm FPGAs offers an unprecedented combination of low power, high functionality, and low cost. The architecture consists of up to 120K vertically arranged logic elements (LEs), 4 Mbits of embedded memory arranged as 9-Kbit (M9K) blocks, embedded multipliers, and phase-locked loops (PLLs) that are surrounded by I/O elements (IOEs), as shown in Figure 1. A highly efficient interconnect and low-skew clock network provides connectivity between each of these structures for clock and data signals.
Figure 1. Cyclone III Floorplan
| Key Features |
Connectivity |
|
|
|
| Market Specific Features |
|
|
|
|
Related Links
|
 Next Steps
Buy Now
Support
Documentation
|
Literature
> 
