Cyclone III Device I/O Connectivity
With Cyclone® III FPGAs, you have the flexibility to implement a wide variety of I/O standards on your board. Intellectual property (IP) cores and the Quartus® II design software which includes tools such as SOPC Builder, TimeQuest timing analyzer, and the Pin Planner that aid in ease of use and rapid integration.
| Table 1. Cyclone III Device I/O Connectivity Overview |
| Feature |
Details |
| Flexible I/O Buffers |
- Supports a wide variety of I/O
|
| LVDS Support on all I/O Banks |
- Dedicated differential output buffers on side I/O banks support LVDS transmit at up to 840 Mbps, no external resistors required on the transmit side
- Top and bottom I/O banks support LVDS transmit at 640 Mbps using a simple series resistor network
- 875 Mbps LVDS receive supported on all I/O banks
|
| Double Data Rate (DDR) Support on all I/O Banks |
- High-performance DDR I/O on top banks and bottom banks
- Supports SDR, DDR, DDR2, and QDRII external memory interfaces
- DDR2 interfaces supported at up to 400 Mbps with easy-to-implement auto-calibrating PHY to ease timing closure
|
| Independent Banks |
- Eight independent user I/O banks provide flexible and efficient pin usage
- Common bank structure for vertical migration
|
Differential Signaling
Cyclone III device I/O pins support fast DC-coupled transmit and receive channels on the side I/O with additional lower speed LVDS support on the top and bottom banks. Cyclone III device high-speed LVDS I/O pins are ideal interfaces for applications such as displays, and video and image processing.
Figure 1. Differential LVDS Buffers.
| Table 2. Cyclone III Device Differential Signaling I/O Feature Overview |
| Feature |
Details |
| High-Speed Differential |
- Dedicated differential buffers
|
| Various Differential I/O Standards |
- Supports LVDS for high-speed applications
- Dedicated output buffers for LVDS, RSDS, and mini-LVDS outputs for display column driver interface in flat panel display links. No series external resistor networks required
- PPDS for liquid crystal display (LCD) television/monitor interfaces
|
Single-Ended I/O Support
Cyclone III device I/O pins support single-ended I/O standards such as LVTTL, LVCMOS, SSTL, HSTL, PCI and PCI-X.
| Table 3. Cyclone III Device Single-Ended I/O Feature Overview |
| Feature |
Details |
| Single-Ended I/O |
- Programmable slew rate and drive strength
- On-chip series termination (OCT) with and without calibration at device power up
|
For more information on OCT see Termination Solutions in Cyclone III Devices.
| Table 4. Differential and Single Ended I/O support |
| I/O Standards |
Typical Application |
Comments |
| Differential I/O |
| LVDS |
Chip-to-Chip |
Dedicated and Pseudo |
| RSDS Mini-LVDS, PPDS |
Display |
Transmit Only |
| LVPECL |
General Purpose |
Clock Inputs Only |
| Single-Ended I/O |
| 3.0-V/2.5-V/1.8-V LVTTL |
General Purpose |
Impedance Matching |
| 3.0-V/2.5-V/1.8-V/1.5-V/1.2-V LVCMOS |
General Purpose |
Impedance Matching |
| SSTL-2 Class I & II |
Memory |
Series OCT |
| SSTL-18 Class I & II |
Memory |
Series OCT |
| 1.8-V/1.5V/1.2-V HSTL I & II |
Memory |
Series OCT |
| 3.0-V PCI |
PC, Embedded |
Impedance Matching |
| 3.0-V PCI-X 1.0 |
PC, Embedded |
Impedance Matching |
For more information on I/O standards see the Cyclone III Device I/O Features (PDF) chapter of the Cyclone III Device Handbook (PDF).
High-Speed External Memory Interface Support
Cyclone III device I/O pins are designed to support existing and popular external memory standards such as DDR, DDR2, and QDRII.
| Table 5. Cyclone III Device External Memory Interfaces I/O Feature Overview |
| Feature |
Details |
| External Memory Support |
- Auto-calibrating PHY interfaces to implement up to 200-MHz DDR2 interfaces
- Dedicated DDR output for enhanced double-data rate I/O timing
- DDR2/DDR available on all sides to ease PCB layout constraints
- On-chip series termination to reduce board cost for DDR/DDR2 memory systems
|
| Table 6. External Memory Interface Performance |
| Memory Standard |
I/O Standard |
| DDR SDRAM |
SSTL-2 |
| DDR2 SDRAM |
SSTL-1.8 |
| QDRII |
1.8v / 1.5v HSTL |
For more information about external memory interfaces on Cyclone III FPGAs, see Altera's External Memory Solution Center and the External Memory Interfaces in Cyclone III Devices (PDF) chapter of the Cyclone III Device Handbook (PDF).
Signal Integrity
Cyclone III FPGAs include several features to help manage and deliver good signal integrity:
| Table 7. Cyclone III FPGA Signal Integrity I/O Feature Overview |
| Feature |
Details |
| Signal Integrity |
- 12:1:1 User I/O to power/ground ratio
- Adjustable slew rates
- Optimized on-die decoupling
- Series OCT
|
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